Sharif Digital Repository

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three contiguous errors. To recover the erroneous register value, two distinct cache memories are utilized for storing the redundant copy of the vulnerable registers, one for short lived registers and the other one for long lived registers. The proposed method has two key advantageous as compared to fully ECC protected... 

This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline's registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures. © 2008 IEEE  

In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

This paper presents a Data Width-aware Register file Protection (DWRP) technique to cope with Multiple Bit Upsets (MBUs) occurring in the register file of embedded processors. The DWRP technique has been proposed based on the fact that there are often a significant number of bits in the register file, which are not fully occupied by data. The DWRP technique efficiently exploits these available free bits for reliability enhancement purposes. In this regard, every register is equipped with three extra tag bits to specify the amount of available free bits in a register. Then the appropriate parity or hamming code is used based on the information of the tag field to protect the register file... 

Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme... 

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this article, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the... 

This paper presents a cost-efficient technique to jointly use circuit- and architecture-level techniques to protect an embedded processor's register file against soft errors. The basic idea behind the proposed technique is robust register caching (RRC), which creates a cache of the most vulnerable registers within the register file in a small and highly robust cache memory built from circuit-level single-event-upset-protected memory cells. To guarantee that the most vulnerable registers are always stored in the robust register cache, the average number of read operations during a register's lifetime is used as a metric to guide the cache replacement policy. A register is vulnerable to soft... 

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in... 

Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an...