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replacement-algorithm
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Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits
, Article Journal of Supercomputing ; Volume 75, Issue 7 , 2019 , Pages 3945-3974 ; 09208542 (ISSN) ; Ahmadpour, I ; Ardebili, M ; Farbeh, H ; Sharif University of Technology
Springer New York LLC
2019
Abstract
Emerging non-volatile memories (NVMs) are known as promising alternatives to SRAMs in on-chip caches. However, their limited write endurance is a major challenge when NVMs are employed in these highly frequently written caches. Early wear-out of NVM cells makes the lifetime of the caches extremely insufficient for nowadays computational systems. Previous studies only addressed the lifetime of data part in the cache. This paper first demonstrates that the age bits field of the cache replacement algorithm is the most frequently written part of a cache block and its lifetime is shorter than that of data part by more than 27×. Second, it investigates the effect of age bits wear-out on the cache...
LER: Least-error-rate replacement algorithm for emerging STT-RAM caches
, Article IEEE Transactions on Device and Materials Reliability ; Volume 16, Issue 2 , 2016 , Pages 220-226 ; 15304388 (ISSN) ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation....
Enhancing Performance of Replacement Policy in Operating System Page Cache for I/O Intensive Workloads
, M.Sc. Thesis Sharif University of Technology ; Asadi, Hossein (Supervisor)
Abstract
Due to the increasing use of data storage systems and volume of digital data, fast information access and retrieval has significant effect on performance of storage-bound systems. Operating systems utilize the spare space in the main memory as a cache to speed up access to the storage subsystem. Due to the large performance gap between hard disk and main memory, any improvement in this caching layer can greatly affect the performance of the entire system. Page replacement algorithms are one of the important mechanisms in the virtual memory management layer. Several algorithms have been proposed for the eviction of pages from the virtual memory cache and few of them have also been implemented...
An Improved replacement algorithm in fault-tolerant meshes
, Article SCSC '07: Proceedings of the 2007 Summer Computer Simulation Conference 2007, Part of the 2007 Summer Simulation Multiconference, SummerSim 2007, San Diego, CA, 15 July 2007 through 18 July 2007 ; Volume 1 , 2007 , Pages 443-448 ; 9781622763580 (ISBN) ; Movaghar, A ; Sadrmousav, M ; Sharif University of Technology
2007
Abstract
Since the failure of resources fatally affects processor allocation, a fault tolerant service is essential in the interconnection networks. In this paper, a new fault tolerant method is proposed and evaluated in the hybrid processor allocation scheme, which we have introduced in our previous work. Our task consists of two independent phases. First, the allocation process executes to allocate an efficient set of processors to the requested submesh. The second phase comes to work when the faulty nodes are detected in the allocated spaces. The selected processor allocation scheme allows jobs to be executed without waiting, provided that the number of processors is sufficient in the system and...