Sharif Digital Repository

This paper describes a sign-sign least-mean squares (LMS) technique to calibrate gain and phase errors in the signal path of a Weaver image-reject receiver. The calibration occurs at startup and the results are stored digitally, allowing continuous signal reception thereafter. Fabricated in a standard digital 0.25-μm CMOS technology, the receiver achieves an image-rejection ratio of 57 dB after calibration, a noise figure of 5.2 dB, and a third-order input intercept point of -17 dBm. The circuit consumes 55 mW in calibration mode and 50 mW in normal receiver mode from a 2.5-V power supply. The prototype occupies an area of 1.23 × 1.84 mm2  

This paper presents a low voltage low noise open loop automatic amplitude control method for voltage-controlled oscillators (VCO's). In this method a feedback mechanism keeps the VCO at its optimum amplitude over temperature and process variations and then the loop is broken to avoid noise injection form the control circuitry to the VCO. The loop does not add extra noise to the VCO. Based on the proposed method, a low voltage low noise LC-VCO was designed for a low phase noise application in TSMC 0.18 micron RFCMOS technology. Simulations show considerable improvement in the phase noise with the application of the proposed method  

The continued migration to smaller nanometer geometries brought fundamental limits to traditional on-chip hard wires performance. According to the International Technology Roadmap for Semiconductor (ITRS), feature size shrinking leads an increase in the operating frequency of RFCMOS devices. Thus, new interconnect methodologies such as radio frequency (RF) wireless can be employed on future chips projected for intra-chip wireless data communications. The size of Si integrated antenna in these frequencies will be several millimetres and the antenna length will be decrease by frequency increasing. In this paper, we have proposed an optimum radiation pattern achieved by a phased array (PA)... 

In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires