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SMART: a scalable mapping and routing technique for power-gating in NoC routers
, Article 2017 11th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, 19 October 2017 through 20 October 2017 ; 2017 ; 9781450349840 (ISBN) ; Kamali, H. M ; Hessabi, S
Abstract
Reducing the size of the technology increases leakage power in Network-on-Chip (NoC) routers drastically. Power-gating, particularly in NoC routers, is one of the most efficient approaches for alleviating the leakage power. Although applying power-gating techniques alleviates NoC power consumption due to high proportion of idleness in NoC routers, since the timing behavior of packets is irregular, even in low injection rates, performance overhead in power-gated routers is significant. In this paper, we present SMART, a Scalable Mapping And Routing Technique, with virtually no area overhead on the network. It improves the irregularity of the timing behavior of packets in order to mitigate...