Sharif Digital Repository

RT-level techniques are one of the most important categories of techniques employed for decreasing power consumption in digital systems. These techniques are usually applied in the HDL description of the system, however some of them are applicable automatically by the synthesis tools. Some of the most commonly used RT-level techniques include Operand isolation, Clock gating, Concurrency & Redundancy, Pre-computation and Pipeline for low power. However these techniques have been mostly employed in ASIC designs, and FPGAs have scarcely been addressed. Application of these techniques on FPGAs might need special considerations, since resources on FPGAs are inherently different than their ASIC...