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sample-and-hold
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Compensating interpolation distortion by new optimized modular method
, Article 2011 18th International Conference on Telecommunications, ICT 2011 ; 2011 , Pages 346-350 ; 9781457700248 (ISBN) ; Tofighi, M ; Marvasti, F ; IBM Cyprus; University of Cyprus; Cyprus Tourism Organisation ; Sharif University of Technology
Abstract
A modular method was suggested before to recover a band limited signal from the sample and hold and linearly interpolated (or, in general, an nth-order-hold) version of the regular samples. In this paper a novel approach for compensating the distortion of any interpolation based on modular method has been proposed. In this method the performance of the modular method is optimized by adding only some simply calculated coefficients. This approach causes drastic improvement in terms of signal-to-noise ratios with fewer modules compared to the classical modular method. Simulation results clearly confirm the improvement of the proposed method and also its superior robustness against additive...
Image inpainting using iterative methods
, Article 4th International Conference on Signal Processing and Communication Systems, ICSPCS'2010 - Proceedings, 13 December 2010 through 15 December 2010, Gold Coast, QLD ; 2010 ; 9781424479078 (ISBN) ; Marvasti, F ; Pourmohammad, A ; Sharif University of Technology
2010
Abstract
Noise interference and data loss are two major problems that affect the processing results of image data transmission and storage. Restoration of the lost information of an image based on the existing information is the essence of inpainting. In this paper a new algorithm based on Sample and Hold interpolation and Iteration is proposed for reconstructing damaged images from existing regions and is compared to some other methods. The experimental results show the superiority of the visual quality and PSNR performance of the proposed method. It is observed that this approach can efficiently fill in the holes with visually plausible information
A high speed, high resolution, low voltage currentmode sample and hold
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 1417-1420 ; 02714310 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE
A low voltage, high speed current mode sample and hold for high precision applications
, Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 1 , 2005 , Pages 269-272 ; 0780390660 (ISBN); 9780780390669 (ISBN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
This paper presents a zero-voltage switching current mode sample and hold(S/H) circuit. The proposed S/H has 12 bit linearity at 180MHz sampling rate for 1.5v supply voltage. The S/H circuit is designed for 0.18μm CMOS technology
A 1.5V 150MS/s current-mode sample-and-hold circuit
, Article 2005 European Conference on Circuit Theory and Design, Cork, 28 August 2005 through 2 September 2005 ; Volume 2 , 2005 , Pages 91-94 ; 0780390660 (ISBN); 9780780390669 (ISBN) ; Rajaee, O ; Jahanian, A ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power
10-Bit 500-MS/s Pipelined Analog to Digital Converter
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to...
A closed-form transfer function for sample and hold master slave sampling filter
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 69, Issue 7 , 2022 , Pages 3159-3163 ; 15497747 (ISSN) ; Sarvari, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2022
Abstract
A switched capacitor circuit frequently appears in literature in form of sample and hold or master-slave sampling filter. We call this block Sample and Hold Master-Slave Sampling Filter (SH-MSSF). Considering the time varying nature of this circuit it is difficult to predict its behavior, though it looks like a very simple circuit. So there exists no formula describing its function in all of its applications. In this brief, we present a closed-form transfer function, explaining the operation of SH-MSSF, based on state-space analysis. Then by interpolating an infinite number of such transfer functions a continuous-time formula is derived that can exactly model the behavior of this (Linear...