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A reconfigurable fault-tolerant routing algorithm to optimize the network-on-chip performance and latency in presence of intermittent and permanent faults
, Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors ; 2011 , Pages 433-434 ; 10636404 (ISSN) ; 9781457719523 (ISBN) ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
Abstract
As the semiconductor industry advances to the deep sub-micron and nano technology points, the on-chip components are more prone to the defects during manufacturing and faults during system operation. Consequently, fault tolerant techniques are essential to improve the yield of modern complex chips. We propose a fault-tolerant routing algorithm that keeps the negative effect of faulty components on the NoC power and performance as low as possible. Targeting intermittent faults, we achieve fault tolerance by employing a simple and fast mechanism composed of two processes: NoC monitoring and route adaption. Experimental results show the effectiveness of the proposed technique, in that it offers...
Plasmonic enhancement of photocurrent generation in two-dimensional heterostructure of WSe2/MoS2
, Article Nanotechnology ; Volume 32, Issue 32 , 2021 ; 09574484 (ISSN) ; Esfandiar, A ; Sharif University of Technology
IOP Publishing Ltd
2021
Abstract
Enhancing the photoresponse of single-layered semiconductor materials is a challenge for high-performance photodetectors due to atomically thickness and limited quantum efficiency of these devices. Band engineering in heterostructure of transition metal chalcogenides (TMDs) can sort out part of this challenge. Here, we address this issue by utilizing the plasmonics phenomenon to enrich the optoelectronics property of the WSe2/MoS2 heterojunction and further enhancement of photoresponse. The introduced approach presents a contamination-free, tunable and efficient way to improve light interactions with heterojunction devices. The results showed a 3600-fold enhancement in photoresponsivity and...
From continuous to quantized charging phenomena in few nanocrystals MOS structures
, Article 11th International Autumn Meeting on Gettering and Defect Engineering in Semiconductor Technology, GADEST 2005, 25 September 2005 through 30 September 2005 ; Volume 108-109 , 2005 , Pages 25-32 ; 10120394 (ISSN); 9783908451136 (ISBN) ; Shalchian, M ; Grisolia, J ; Bonafos, C ; Atarodi, S. M ; Claverie, A ; Pichaud B ; Claverie A ; Alquier D ; Richter H ; Kittler M ; Richter H ; Kittler M ; Sharif University of Technology
Trans Tech Publications Ltd
2005
Abstract
In this paper, we present a study on the contribution of silicon nanocrystals to the electrical transport characteristics of large (100 µ x 100 µm) and small (100 nm x 100 nm) metaloxide- semiconductor (MOS) capacitors at room temperature. A layer of silicon nanocrystals is synthesized within the oxide of these capacitors by ultra-low energy ion implantation and annealing. Several features including negative differential resistance (NDR), sharp current peaks and random telegraph signal (RTS) are demonstrated in the current-voltage and current-time characteristics of these capacitors. These features have been associated to charge storage in silicon nanocrystals and to the resulting Coulomb...
ANMR: aging-aware adaptive N-modular redundancy for homogeneous multicore embedded processors
, Article Journal of Parallel and Distributed Computing ; Volume 109 , 2017 , Pages 29-41 ; 07437315 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
Abstract
Advances in semiconductor technology have made integration of multiple processing cores into one single die a promising trend towards increasing processing performance, lowering power consumption, and increasing reliability for embedded systems. Multicore processors, due to their intrinsic redundancies, are good choices for critical embedded systems for which the reliability is a crucial component. In this paper, an aging-aware adaptive fault tolerance method for DVFS-enabled multicore processors is presented. The analytical results show 3 to 6 order of magnitude increase in reliability of the system without addition of cores or redundant software. By using an aging-aware approach, the...
High-Photoresponsive backward diode by two-dimensional SnS2/Silicon heterostructure
, Article ACS Photonics ; Volume 6, Issue 3 , 2019 , Pages 728-734 ; 23304022 (ISSN) ; Esfandiar, A ; Iraji Zad, A ; Hosseini Shokouh, S. H ; Mahdavi, S. M ; Sharif University of Technology
American Chemical Society
2019
Abstract
Two-dimensional semiconductor materials can be combined with conventional silicon-based technology and sort out part of the future challenges in semiconductor technologies due to their novel electrical and optical properties. Here, we exploit the optoelectronics property of the silicon/SnS2 heterojunction and present a new class of backward diodes using a straightforward fabrication method. The results indicate an efficient device with fast photoresponse time (5-10 μs), high photoresponsivity (3740 AW-1), and high quantum efficiency (490%). We discuss device behavior by considering the band-to-band tunneling model and band bending characteristics of the heterostructure. This device structure...
An optimal analytical solution for maximizing expected battery lifetime using the calculus of variations
, Article Integration ; Volume 71 , March , 2020 , Pages 86-94 ; Ejlali, A ; Sharif University of Technology
Elsevier B.V
2020
Abstract
The exponential growth in the semiconductor industry and hence the increase in chip complexity, has led to more power usage and power density in modern processors. On the other hand, most of today's embedded systems are battery-powered, so the power consumption is one of the most critical criteria in these systems. Dynamic Voltage and Frequency Scaling (DVFS) is known as one of the most effective energy-saving methods. In this paper, we propose the optimal DVFS profile to minimize the energy consumption of a battery-based system with uncertain task execution time under deadline constraints using the Calculus of Variations (CoV). The contribution of this work is to analytically calculate the...
Evolution of quantum electronic features with the size of silicon nanoparticles embedded in a sio2 layer obtained by low energy ion implantation
, Article 11th International Autumn Meeting on Gettering and Defect Engineering in Semiconductor Technology, GADEST 2005, 25 September 2005 through 30 September 2005 ; Volume 108-109 , 2005 , Pages 71-76 ; 10120394 (ISSN); 9783908451136 (ISBN) ; Shalchian, M ; Benassayag, G ; Coffin, H ; Bonafos, C ; Dumas, C ; Atarodi, S. M ; Claverie, A ; Pichaud B ; Claverie A ; Alquier D ; Richter H ; Kittler M ; Richter H ; Kittler M ; Sharif University of Technology
Trans Tech Publications Ltd
2005
Abstract
In this paper, we have studied the evolution of quantum electronic features with the size of silicon nanoparticles embedded in an ultra-thin SiO2 layer. These nanoparticles were synthesized by ultralow energy (1 KeV) ion implantation and annealing. Their size was modified using the effect of annealing under slightly oxidizing ambient (N2+O2). Material characterization techniques including transmission electron microscopy (TEM) Fresnel imaging and spatially resolved electron energy loss spectroscopy (EELS) have been used to evaluate the effects of oxidation on structural characteristics of nanocrystal layer. Electrical transport characteristics have been measured on few (less than two...
Charge controlling in nanoscale shielded channel DG-MOSFET: A quantum simulation
, Article 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, Mumbai, 16 December 2007 through 20 December 2007 ; 2007 , Pages 127-129 ; 9781424417285 (ISBN) ; Orouji, A. A ; Faez, R ; Sharif University of Technology
2007
Abstract
Nanoscale Shielded channel transistors are investigated by solving the two-dimensional Poisson equation self-consistently with ballistic quantum transport equations for first time. We present self-consistent solutions of ultrathin body device structures to investigate the effect of electrically shielded channel region which impose charge controlling in the channel region on the characteristics of nanoscale DG-MOSFET. The simulation method is based on Nonequlibrium Green's Function (NEGF). Starting from a basic structure with a gate length of 10 nm, the effect of gate length variation on the performance of the device has been investigated. © 2007 IEEE
Two-dimensional quantum simulation of scaling effects in ultrathin body MOSFET structure: NEGF approach
, Article 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, Mumbai, 16 December 2007 through 20 December 2007 ; 2007 , Pages 240-242 ; 9781424417285 (ISBN) ; Dehdashti, N ; Faez, R ; Sharif University of Technology
2007
Abstract
For the first time, we present self-consistent solution of ultrathin body device structures to investigate the device parameters variation on the characteristics of nanoscale MOSFET. Our two dimensional (2-D) device simulator Is based on Nonequlibrium Green's Function (NEGF) forma lism. Starting from a basic structure (DG-MOSFET) with a gate length of 10 nm, variation of gate length, channel thickness, gate oxide parameters was carried out in connection with the numerical calculation of device characteristics. In this work Quantum transport equations are solved in 2-D by NEGF method in active area of the device to obtain the charge density and Poisson's equation is solved in entire domain of...