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    A compact hybrid current/voltage sense amplifier with offset cancellation for high-speed SRAMs

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 19, Issue 5 , 2011 , Pages 883-894 ; 10638210 (ISSN) Sharifkhani, M ; Rahiminejad, E ; Jahinuzzaman, S. M ; Sachdev, M ; Sharif University of Technology
    A hybrid current/voltage sense amplification scheme is proposed for high speed SRAMs. The scheme includes an offset cancellation technique which makes it robust against the current sense amplifier (CSA) mismatch. The offset cancellation allows for fast open loop operation of the differential CSA. A fourfold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. Thanks to its automatic turn off nature, the proposed CSA incurs zero static power without an auxiliary turn off circuit. The reduction of the charge redistribution on the bitlines offers a low bitline dynamic power consumption as well. In this work, the... 

    An Adaptive Low-Power Sense Amplifier with Offset-Cancellation for High-Speed SRAM

    , M.Sc. Thesis Sharif University of Technology Attarzadeh, Hourie (Author) ; Sharifkhani, Mohammad (Supervisor)
    A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. This reinforces the need to design a more compact SRAM. With the increase in the processors speed, memories speed needs to be increased to enhance the overall throughput. Current Sense Amplifiers have partially solved the problem. However the area occupied by these amplifiers is still a large amount. The input offset is also not negligible. Due to their cascode configuration, these circuits cannot be scaled with the voltage scaling. In this thesis we proposed a new hybrid sense amplifier with an added phase, so the input offset can be cancelled with a large... 

    A 32kb 90nm 10T-cell sub-threshold SRAM with improved read and write SNM

    , Article 2013 21st Iranian Conference on Electrical Engineering ; May , 2013 ; 9781467356343 (ISBN) Hassanzadeh, S ; Zamani, M ; Hajsadeghi, K ; Sharif University of Technology
    The constraints of power saving have compelled SRAM designers to consider sub-threshold area as a viable choice. The biggest barrier of this progress is the stability of SRAM's cells and the correct operations. In this paper a 10T cell structure has been proposed with 90% read and 50% write SNM improvement in comparison to the conventional 6T cell. The hold SNM value is about the 6T cell SRAM. Also using differential read method in the proposed structure causes high read performance and using simpler sense amplifier. The symmetric configuration of this structure helps the SRAM has simpler layout and lower transistor mismatch. Using 90nm TSMC CMOS, 32kb 10T cell SRAM in sub-threshold area is... 

    PF-DRAM: A precharge-free DRAM structure

    , Article 48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, 14 June 2021 through 19 June 2021 ; Volume 2021-June , 2021 , Pages 126-138 ; 10636897 (ISSN); 9781665433334 (ISBN) Rohbani, N ; Darabi, S ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Although DRAM capacity and bandwidth have increased sharply by the advances in technology and standards, its latency and energy per access have remained almost constant in recent generations. The main portion of DRAM power/energy is dissipated by Read, Write, and Refresh operations, all initiated by a Precharge phase. Precharge phase not only imposes a large amount of energy consumption, but also increases the delay of closing a row in a memory block to open another one. By reduction of row-hit rate in recent workloads, especially in multi-core systems, precharge rate increases which exacerbates DRAM power dissipation and access latency. This work proposes a novel DRAM structure, called... 

    A scalable offset-cancelled current/voltage sense amplifier

    , Article ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 3853-3856 ; 9781424453085 (ISBN) Attarzadeh, H ; SharifKhani, M ; Jahinuzzaman, S. M ; Sharif University of Technology
    the application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with... 

    Design and Simulation of Phase Detector and Other Digital Circuits of an All Digital Frequency Synthesizer to Decrease Phase Noise and Lock Time

    , M.Sc. Thesis Sharif University of Technology Ensafdaran, Masoud (Author) ; Atarodi, Mojtaba (Supervisor)
    In this thesis, An All Digital Frequency Synthesizer for use in RF applications is designed in 180nm CMOS. Different blocks such as Phase detector, Loop filter and Loop counter is designed. Finally, an All Digital Frequency Synthesizer is modeled using this circuits and an Digitally controlled oscillator model and is designed for GSM. In this thesis a new method is proposed to noise shape the quantization noise of the time to digital converter. The Time to Digital Converter has 7mW power consumption for 0ns to 1ns input range. Using this noise shaping method, quantization noise is reduced about 20dB. Also, limit cycle related spurs is reduced significantly using first order and second order... 

    A Novel Bitline Leakage-Free Current Sense Amplifier with Offset Cancelation for Sub-Threshold SRAM

    , M.Sc. Thesis Sharif University of Technology Zamani, Milad (Author) ; Sharifkhani, Mohammad (Supervisor)
    A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. The fast growth of battery-operated portable applications has compelled the SRAM designers to consider subthreshold operation as a viable choice to reduce the power consumption. In most such applications, the speed of the SRAM is not the challenging parameter therefore the thrust toward low power design influence the design choices in various parts of the SRAM architecture. With technology scaling to the nanometer, Bitline leakage current and offset voltage deteriorate SRAM reading performance since SRAM cell current is close to the Bitline leakage current.... 

    An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier

    , Article Microelectronics Journal ; Vol. 45, issue. 6 , 2014 , p. 781-792 Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
    A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a... 

    A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM

    , Article Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 ; 2013 , Pages 104-107 ; 9781467360388 (ISBN) Zamani, M ; Hassanzadeh, S ; Hajsadeghi, K ; Saeidi, R ; Sharif University of Technology
    The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense...