Sharif Digital Repository

This paper presents a new method for design of Variable Fractional Delay (VFD) FIR digital filters using Genetic Algorithm. In this method, each sub-filter of Farrow structure is designed separately with defined accuracy and bandwidth. Also, a variable mutation probability is employed, which improves the accuracy of the solution. Compared with exiting methods, it reduces the computational complexity and enhances the design flexibility. Sum-of-power-of-two (SOPOT) representation is applied to the filter coefficients. Therefore, SOPOT coefficients of Farrow structure are determined using a simple Genetic Algorithm without recourse to computational techniques. Using the SOPOT representation,... 

A new approach for data detection in fast fading channels is proposed. By using a combination of Rake receiver and sequential detection for fast fading channels, it is shown that system performance can be improved without prior knowledge of the channel. As will be shown in this paper, by combining spread spectrum signaling and sequential detection it is possible to exploit the time-frequency diversity of fast fading channels in a novel way. It is shown by simulation that combination of sequential detection and Rake receiver can effectively improve system performance, compared with equal gain combining  

A5/1 is the strong version of the encryption algorithm on GSM (Global System for Mobile communications) used in many countries. It is constructed of a combination of three LFSRs (Linear Feedback Shift Registers) with irregular clocking manner. One of the most practical attacks against this algorithm is time-memory trade-off attack, which is based on birthday paradox. The goal of this attack is to find any intersection between precomputed LFSRs states set and set of states generating the output bits in the actual execution of the algorithm. In order to increase feasibility of this attack, the biased birthday attack was introduced. In this attack special states producing a specific pattern in... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

Purpose - Digital Delta Sigma Modulator (DDSM) is used widely in electronic circuits including Radars, class-D power amplifiers and fractional frequency synthesizers. The purpose of this paper is to propose an implementation for MASH DDSMs named as Multi Modulus Reduced Complexity (MMRC) architecture. Design/methodology/approach - This architecture will use a very simple pseudorandom Linear Feedback Shift Register (LFSR) dither signal with period N-d to randomize the digital MMRC modulator used for fractional frequency synthesizers. Using error masking methodology, the MMRC modulator can decrease the hardware consumption and increase accuracy of the fractional frequency synthesizer. Rules... 

Communication wire delay between multiple blocks is becoming a critical issue in System on Chip (SoC) design. Scheduling-based Latency-Insensitive Design (LID) is a method to alleviate wire delays by utilizing a central scheduling scheme for periodic clock gating of the blocks. The scheduling scheme resides in shift registers as sequences of '1' and '0' bits. In many systems, these sequences are too long, and have large area overhead. This problem indisposes the implementation of the scheduling based protocol. This paper proposes an algorithm that finds sequences with shorter lengths in comparison with the prior algorithm. On synthetic/random test cases, the algorithm gives 45% reduction on... 

This paper presents several efficient architectures of dynamic/static edge-triggered flip-flops with a compact embedded logic. The proposed structure, which benefits from the overlap period, fixes most of the drawbacks of the dynamic logic family. The design issues of setting the appropriate overlap period for this architecture are explained. The proposed overlap-based approach is compared with several state-of-the-art dynamic/static logic styles in implementing a 4-bit shift register and an odd-even sort coprocessor using different CMOS technologies. The simulation results showed that the overlap-based logic cells become much more efficient when the complexity of their embedded logic... 

A correlation measuring tool for an endogenous pulsed neutron source experiment is developed in this work. Paroxysmal pulses generated by a bursts of neutron chains are detected by a 10-kbit embedded shift register with a time resolution of 100 ns. The system is implemented on a single reprogrammable device making it a compact, cost-effective instrument, easily adaptable for any case study. The system was verified experimentally in the Esfahan heavy-water zero power reactor (EHWZPR). The results obtained by the measuring tool are validated by the Feynman-α experiment, and a good agreement is seen within the boundaries of statistical uncertainties. The theory of the methods is briefly...