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An 8-bit 160 MS/s folding-interpolating adc with optimizied active averaging/interpolating network
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 6150-6153 ; 02714310 (ISSN) ; Movahedian, H ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE
An area and power optimization technique for CMOS bandgap voltage references
, Article Analog Integrated Circuits and Signal Processing ; Volume 62, Issue 2 , 2010 , Pages 131-140 ; 09251030 (ISSN) ; Chahardori, M ; Khodaverdi, A ; Sharif University of Technology
2010
Abstract
This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in...
A low power, low phase noise, square wave LC quadrature VCO and its comprehensive analysis for ISM band
, Article AEU - International Journal of Electronics and Communications ; Volume 65, Issue 5 , 2011 , Pages 458-467 ; 14348411 (ISSN) ; Torkzadeh, P ; Behmanesh, B ; Sharif University of Technology
Abstract
This paper presents a phase-noise reduction technique for voltage-controlled oscillators (VCOs) using a harmonic tuned (HT) LC tank. The phase-noise suppression is achieved through almost rectangular-shaped VCO oscillating signal which effectively maximizes oscillating signal slope at zero crossing points resulting in-phase-noise degradation. In addition, by shortening down converted noise power around oscillating signal second harmonic, more phase-noise suppression has been achieved. A comprehensive analysis for frequency and amplitude deviations as high as 20% for third harmonic and its effect on output phase-noise suppression has been discussed. In the followings, a comprehensive analysis...