Sharif Digital Repository

In this article, a methodology is developed to solve an interval and a fractional interval programming problem by converting into a non-interval form for second order cone constraints, with the objective function and constraints being interval valued functions. We investigate the parametric and non-parametric forms of the interval valued functions along with their convexity properties. Two approaches are developed to obtain efficient and properly efficient solutions. Furthermore, the efficient solutions or Pareto optimal solutions of fractional and non-fractional programming problems over R + n S (0) are also discussed. The main idea of the present article is to introduce a new concept for... 

In this paper, we present results of our experiments in implementation of a widely used DSP primitive on a programmable SoC (System-on-a-Chip) Device. The DSP primitive is a 16-bit digital FIR filter which we implemented on Triscend E5 CSoC® family. Experimental results show that by properly breaking the DSP task into hardware and software parts, one can achieve higher throughput compared to DSP processor implementations, while having more flexibility and less time-to-design compared to full-hardware realizations. Programmable SoC device facilitates rapid design-space exploration, which we employed to optimize our mixed hardware-software architecture. We compared our filter throughput to... 

Suppressor of cytokine signalling (SOCS) family comprises a group of proteins that impede JAK/STAT signalling, thus being involved in the pathogenesis of immune-related conditions. In the present work, we aimed at identification of the role of SOCS genes in the pathogenesis of periodontitis through evaluation of their expression levels both in the circulation and in the affected tissues of patients. Thus, we measured expression levels of SOCS1-3 and SOCS5 transcripts in the blood and gingival samples of patients with periodontitis in comparison with control samples obtained during dental crown lengthening. Expressions of SOCS1, SOCS2, SOCS3 and SOCS5 genes were similar between gingival... 

In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing  

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches  

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Real-time (RT) communication support is a critical requirement for many complex embedded applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper, we present novel methods to efficiently calculate worst case bandwidth and latency bounds for RT traffic streams on wormhole-switched NoCs with arbitrary topology. The proposed methods apply to best-effort NoC architectures, with no extra hardware dedicated to RT traffic support. By applying our methods to several realistic NoC designs, we show substantial improvements (more than 30 percent in bandwidth and 50 percent in latency, on average) in bound tightness with respect to existing approaches  

By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents an improved scheme for generating pre-computed test patterns in core-based systems on chip. This approach reduces the number of pre-computed test patterns and as the result, test application time (TAT) will be decreased.... 

Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh topologies, other structures can also be considered especially in 3D VLSI design. The Kautz topology is one of the interconnection architectures for multiprocessors. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the Kautz topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation. ©2008 IEEE  

In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE  

We study the trade-off between throughput and memory footprint of embedded software that is synthesized from acyclic static dataflow (task graph) specifications targeting distributed memory multiprocessors. We identify iteration overlapping as a knob in the synthesis process by which one can trade application throughput for its memory requirement. Given an initial processor assignment and non-overlapped task schedule, we formally present underlying properties of the problem, such as constraints on a valid iteration overlapping, maximum possible throughput, and minimum memory footprint. Moreover, we develop an effective algorithm for generation of a rich set of design points that provide a... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement  

This paper presents a decentralized load sharing and power management method for an islanded microgrid composed of PV units, battery units and hybrid PV/battery units. The proposed method performs all the necessary tasks such as load sharing among the units, battery charging and discharging and PV power curtailment with no need to any communication among the units. The proposed method is validated experimentally  

Many Networks-on-Chip (NoC) applications exhibit one or more critical traffic flows that require hard Quality of Service (QoS). Guaranteeing bandwidth and latency for such real time flows is crucial. In this paper, we present novel methods to efficiently calculate worst-case bandwidth and latency bounds and thereby provide hard QoS guarantees. Importantly, the proposed methods apply even to best-effort NoC architectures, with no extra hardware dedicated to QoS support. By applying our methods to several realistic NoC designs, we show substantial improvements (on average, more than 30% in bandwidth and 50% in latency) in bound tightness with respect to existing approaches. Copyright 2009 ACM  

This paper proposes a new decentralized power management and load sharing method for a photovoltaic (PV)-based, hybrid single/three-phase-islanded microgrid consisting of various PV units, battery units, and hybrid PV/battery units. The proposed method is not limited to the systems with separate PV and battery units, and power flow among different phases is performed automatically through three-phase units. The proposed method takes into account the available PV power and battery conditions of the units to share the load among them. To cover all possible conditions of the microgrid, the operation of each unit is divided into five states in single-phase units and seven states in three-phase... 

This paper proposes a new decentralized power management and load sharing method for a photovoltaic based islanded microgrid consisting of various photovoltaic (PV) units, battery units and hybrid PV/battery units. Unlike the previous methods in the literature, there is no need to communication among the units and the proposed method is not limited to the systems with separate PV and battery units or systems with only one hybrid unit. The proposed method takes into account the available PV power and battery conditions of the units to share the load among them. To cover all possible conditions of the microgrid, the operation of each unit is divided into five states and modified active... 

This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09- SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering... 

In this paper, we introduce a new Multi-Objective Genetic Algorithm (MOGA) for mapping a given set of intellectual property onto a Network-on-Chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is...