Sharif Digital Repository

The aggressive device scaling and exponential increase in transistor counts on a chip have increasingly made the modern integrated circuits more susceptible to soft errors. Soft errors are caused by strikes from energetic particles such as neutrons and alpha particles. These errors are making a significant impact in the microelectronics industry. An essential step to design a highly reliable digital system with minimal performance and power penalty is Soft Error Rate (SER) estimation of system components.We propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates, flip-flops, and paths of a circuit. Our proposed approach fully... 

In this thesis, we intend to propose low cost SED-tolerant techniques for different compo­ nents of embedded processors core including data path components such as register file and ALU as well as control path components such as control unit. Since the reliability es­ timation is the essential step in design of a fault-tolerant system, we propose fast and accu­ rate analytical soft error rate (SER) estimation techniques in Section 4. The proposed techniques have the ability to measure: 1) the SER of a design; 2) the SER of each indi­ vidual gate and FF, and 3) the SER of a specific path in the design. Using such infor­ mation, designers can selectively protect the vulnerable parts... 

Cache memory is one of the most important parts of the microprocessors. Caches improve performance by bringing data and instructions near the processors and decreasing the access time to data and instructions. But caches are also vulnerable to some kind of error called soft error. When an error happens in a cache, suddenly can propagate throughout the system and affect the integrity and reliability of the overall system. There are actually two types of errors in cache memories, permanent (hard) errors and transient (soft) errors. Previous studies have shown that about 92% of system reboots are initiated by soft-error occurring in cache memory. Soft-errors have two main sources, alpha... 

In recent years, due to various reasons, such as outsourcing, hardware security and trust have become a crucial issue and confrontation with hardware Trojan has become one of the important part of it. Widespread usage of reconfiguration devices in industry, due to various reasons like low cost design and short time to market, makes these devices appealing for inserting hardware Trojan. Additionally, reconfigurable devices are susceptible to soft errors. Inserting a hardware Trojan in a system by an attacker can leak some information or even cause the system to break down. In previous works, in order to detect hardware Trojan, some methods have been proposed which impose high area and... 

Recent advances in VLSI technologies have enabled current silicon dies to accommodate billions of transistors in the design of very complex System-on-Chips (SoCs). To address the resulting complexity, Network-on-Chips (NoCs) have emerged as a paradigm to design scalable communication architecture to connect the processing cores of an SoC. However, smaller feature sizes, lower voltage levels and higher frequencies in Deep Sub-Micron (DSM) technologies make NoCs highly susceptible to transient faults, e.g., crosstalks, particle strikes, electro-magnetic interferences, and power supply disturbances. Single Event Upsets (SEUs) caused by high energy particle strikes as well as crosstalks are the... 

From small businesses to large organizations and corporations, data is the most valuable and most vulnerable asset. The exponential explosion of digital data, known as Big Data, has evolved data storage industry and mandates new solutions for handling dependability and performance demands. Now Exa-scale datacenters employ millions of storage media that translates to multiple failures per hour. The storage design problem gets more dimensions by the emerge of Non-Volatile Memories (NVMs) and Solid-State Drives (SSDs) that have limited endurance. Both industry and academy continuously struggle to evaluate and improve the dependability of data storage systems and minimize the chance of data... 

Network on chips (NoCs) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chipsincreases the probability of errors and making the reliability a major issue in scaling chips. Soft errors and crosstalk faults are the most important fault sources which can decrease the reliability of NoCs. The probability of Soft errors has increased by about 6 to 7 times by scaling from 130 to 30 nm technology. Since buffers occupy in about 40% to 90% of the area of switches, the probability of a multiple bit upset in a switch buffers is noticeable. In NoC architecture, a packet is broken down into multiple flow control units called... 

With continuous device down-scaling and increase in transistor counts on a chip, complementary metal-oxide-semiconductor (CMOS) technology has become extremely sensitive to soft errors. Soft errors are transient errors caused by energetic particles such as neutrons and alpha particles. An essential step to design a soft error tolerant digital system with minimal performance and power overheads is Soft Error Rate (SER) estimation of system components. Until recently, Single Event Upsets (SEUs) in latches and Filp-Flops (FFs) and Single Event Transients (SETs) in combinational logic parts of digital circuits were regarded as the main effects of particle strikes. However, with the emerging...