Sharif Digital Repository

Non-deterministic finite automata (NFA) are an elementary type of Turing machines with very high processing power. NFA processors provide parallelism at the data and task level because they can be in several different output states in one clock cycle. Implementing such machines with memory is a good strategy because if we consider each of the memory columns as a state, by selecting a row of the memory, we can activate several states at the same time, which is an implementation of NFA. NFA-based automata processors were first introduced by Micron and were very powerful for issues such as pattern matching, DNA sequencing, or regular expressions and, in general, for machine learning topics.... 

Traditional multi-level SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, power consumption, and design complexity. STT-RAM has received increasing attention because of its attractive features:good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/4 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system... 

Emerging non-volatile memory technologies such as Spin- Transfer Torque RAM (STT-RAM) or Resistive RAM (ReRAM) can increase the capacity of the last-level cache (LLC) in a latency and power-efficient manner. These technologies endure between 109 to 1012 writes per cell, making a non-volatile cache (NV-cache) with a lifetime of dozens of years under ideal conditions. However, non-uniformity in writes to different cache lines can considerably reduce the NV-cache lifetime to few months. Writes to cache lines can be made uniformly with wear-leveling. A suitable wear-leveling for NV-cache should not incur high storage and performance overheads. We propose a novel, simple, and effective... 

Spin-Transfer-Torque-RAM (STT-RAM) has recently been widely accepted as a promising replacement for SRAM technology through the technology scaling due to its high density, zero standby power and comparable-to-SRAM read access latency. However, there are two major obstacles to use STT-RAM, namely, high write access latency and energy. In this study, we propose two approaches to solve these challenges in embedded systems. The conventional latency of the STT-RAM write operation is 10ns and lowering the write latency causes the required write current exponentially increase, leading to a larger memory cell area and a shorter memory lifetime. As the first proposed method, we have assessed the... 

Cache memories occupy a large portion of processors chip area. According to academic and industrial reports, the dominant effect of leakage current in less than 40-nm technology nodes has led to serious challenges in scalability and energy consumption of SRAM and DRAM memories. To overcome this challenge, different types of non-volatile memories have been introduced. Among them, Spin-Transfer Torque Random Access Memory (STT-RAM) memory is known as the best candidate to replace SRAM in the cache memories, due to its high density and low access latency. Despite their advantages over SRAMs, several problems in STT-RAM need to be addressed to make it applicable in cache memories. The most... 

On-chip caches are regarded as a solution for increasing performance gap between main memory and CPU. In recent years, with the development in the performance of processing cores, the demands for larger on-chip caches are also increased. With the technology scaling trend, SRAM-based on-chip caches suffer from limited scalability, high leakage power consumption and vulnerability to soft errors. Among emerging non-volatile memories, STT-MRAMs are the most promising alternative for SRAMs in large last-level on-chip caches due to their higher density and near zero leakage power. However, the reliability of STT-MRAMs is threatened by soft and hard errors. Soft errors in STT-MRAMs can be... 

Ever increasing number of on-chip processors coupled with the trend towards rising memory footprints of the programs increases the demand for larger cache and main memory to hide the long latency of disk system. During the last three decades, SRAM- and DRAM-based memory successfully kept pace with this capacity demand by exponential reduction in cost per bit. Feedbacks from industry also confirms that entering sub-20nm technology era with dominant role of leakage power, however, SRAM and DRAM memories are confronting serious scalability and power limitations. To this end, researchers always pursuit some circuit-level and architectural proposals for incorporating non-volatile technologies in... 

Spin-Transfer Torque Magnetic RAM (STT-MRAM) is known as the most promising replacement for SRAM technology in cache memories. Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation-induced particle strikes as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure, read disturbance, and write failure. Despite its high-density, non-volatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM suffers from high error rates. These errors, which are mainly retention failure, read disturbance, and write failure, are the major reliability challenge in STT-MRAM caches.... 

Spin-Transfer Torque Magnetic RAM (STT-MRAM) is the most promising nonvolatile memory to replace SRAM technology in the Last-Level Cache (LLC) due to its benefits such as high density, near-zero cell leakage, and immunity to soft errors.However, due to its high retention failure and read disturbance rates in the downscaled technologies and the low data access rate in the LLC and the high number of read accesses, retention failure and read disturbance have become the main reliability challenges for STT-MRAM cache memory. The existing approaches to overcome these challenges impose significant area and performance overhead or adversely affect the other types of failures. In this thesis, we... 

Due to the high processing capacity of GPGPUs and their requirement to a large and high speed shared memory between thread processors clusters, exploiting Spin-Transfer Torque (STT) RAM as a replacement with SRAM can result in significant reduction in power consumption and linear enhancement of memory capacity in GPGPUs. In the GPGPU (as a many-core) with ability of parallel thread executing, advantages of STT-RAM technology, such as low read latency and high density, could be so effective. However, the usage of STT-RAM will be grantee applications run time reduction and growth threads throughput, when write operations manages and schedules to have least overhead on read operations. The... 

Reliability, performance, and energy consumption are among the most important constraints that should be satisfied in modern processors design. More than 60% of the chip area is occupied by on-chip SRAM memories and they not only contribute in a large fraction of energy consumption, but also are the most error-prone components. Radiation-induced soft errors in on-chip memories are a major concern in modern processors design. Although Single Event Upsets (SEUs) have been known to be the main concern regarding SRAM memory reliability over the past decades, with the continued downscaling of technology, the occurrence rate of Multiple-Bit Upsets (MBUs) is comparable to that of SEUs in today’s... 

With the technology scaling trend in recent years, leakage power has become a major challenge for SRAM-based on-chip memories. According to the recent reports, SRAM-based on-chip memories contribute to more than half of the processors’ power consumption. Accordingly, in recent years, researchers have tried to find an alternative technology for SRAMs in on-chip memories. The International Technology Roadmap for Semiconductors (ITRS) recently announced that STT-MRAMs are the most promising technology to replace SRAMs. While STT-MRAMs benefit from low energy consumption, high endurance, and high density compared to other non-volatile memory technologies, comparing with SRAMs, STT-MRAMs have... 

Today convolutional neural networks (CNN) are very popular due to their high accuracy and robustness. As the size and complexity of CNNs grow, the demand for larger on-chip memories also increases. Given that off-chip access memory has a high cost, one solution is to enlarge on-chip caches by employing emerging multi-level Cell (MLC) STT-RAMs. This memory provides higher capacity at the cost of lower reliability. The root cause of low reliability of MLC STT-RAM is failure of read and write operations. However, MLC STT-RAM and CNNs are perfect matches in the sense that in one hand MLC STT-RAM provides higher capacity, on the other hand CNN can tolerates moderate level of inaccuracy and low...