Sharif Digital Repository

Due to the growing complexity of today's digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and... 

Phase Change Memory (PCM) is an emerging memory technology that has the capability to address the growing demand for memory capacity and bridge the gap between the main memory and the secondary storage. As a resistive memory, PCM is able to store data based on its resistance values. The wide resistance range of PCM makes it possible to store even multiple bits per cell (MLC) rather than a single bit per cell (SLC). Unfortunately, PCM cells suffer from short lifetime. That means PCM cells could tolerate a limited number of write operations, and afterward they tend to permanently stick at a constant value. Limited lifetime is an issue related to PCM memory; hence, in recent years, many studies... 

Main burdens to the DRAM scalability are leakage and charge storage restrictions. Phase Change Memory (PCM) is being known as a promising candidate for the replacement of DRAM among competitive non-volatile memories. However, this memory suffers from low cell reliability due to limited write endurance. This problem can lead to some memory cells permanently stuck at either '0' or '1'. Therefore, a robust error recovery scheme is needed to overcome this problem and recover from hard errors. State-of-the-art solutions apply error correction and recovery techniques at inter-line or intra-line level. Precisely, they can improve PCM endurance either by remapping failed lines to spares (in... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably...