Sharif Digital Repository

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When...