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    Joint mapping of mobility and trap density in colloidal quantum dot solids [electronic resource]

    , Article Journal of ACS nano ; 2013, Vol.7, No. 7, P.5757-5762 Stadler, Philipp ; Sutherland, Brandon R ; Ren, Yuan ; Ning, Zhijun ; Simchi, A. (Arash) ; Thon, Susanna M ; Hoogland, Sjoerd ; Sargent, Edward H ; Sharif University of Technology
    Abstract
    Field-effect transistors have been widely used to study electronic transport and doping in colloidal quantum dot solids to great effect. However, the full power of these devices to elucidate the electronic structure of materials has yet to be harnessed. Here, we deploy nanodielectric field-effect transistors to map the energy landscape within the band gap of a colloidal quantum dot solid. We exploit the self-limiting nature of the potentiostatic anodization growth mode to produce the thinnest usable gate dielectric, subject to our voltage breakdown requirements defined by the Fermi sweep range of interest. Lead sulfide colloidal quantum dots are applied as the active region and are treated... 

    A novel low power 8T-cell sub-threshold SRAM with improved read-SNM

    , Article Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 ; 2013 , Pages 35-38 ; 9781467360388 (ISBN) Hassanzadeh, S ; Zamani, M ; Hajsadeghi, K ; Saeidi, R ; Sharif University of Technology
    2013
    Abstract
    The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is... 

    Influential Factors in the Unstability of SRAM Cell and a Novel Structure for Improvement of Stability

    , M.Sc. Thesis Sharif University of Technology Hasanzadeh, Sina (Author) ; Hajsadeghi, Khosro (Supervisor)
    Abstract
    Embedded SRAM unit is recognized as an important block in the systems on chip. In recent years due to an abrupt increase in the number of such systems which often work with battery, the priority of designing of low power circuits has been increased. Furthermore, increase in the number of transistors in the SRAM and increase in leakage current of MOS transistors with technology scaling have rendered the SRAM into the main energy consumer (from both static and dynamic view).In the writing operation due to the full swing of bit line, the dynamic power forms the main chunk of the consumptive power. The static consumptive power mostly happens due to the leakage current of broken cells in an array... 

    A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2011 , Pages 61-64 ; 02714310 (ISSN) ; 9781424494736 (ISBN) Saeidi, R ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    This paper introduces a Dynamic Read SRAM (DRSRAM) architecture for high-density subthreshold RAM applications. DRSRAM performs a dynamic read operation to overcome the poor stability and bitline leakage problem of 6T SRAM cell in sub-threshold region. It is shown that there is fundamental limit for wordline activation time and recovery time under a given cell mismatch and bitline leakage. To verify the proposed technique, a 64128 bit array of the 6T bit-cell is simulated in 90 nm CMOS technology. The simulation results show a 100% noise margin enhancement at subthreshold region. This design operates down to 300 mV at a 1 MHz clock rate with noise margins as large as 72 mV. This design... 

    Analysis and simulation of asymmetrical nanoscale self-switching transistor

    , Article International Journal of Modelling and Simulation ; 2021 ; 02286203 (ISSN) Horri, A ; Faez, R ; Sharif University of Technology
    Taylor and Francis Ltd  2021
    Abstract
    In this paper, we present a computational study on the electrical behaviour of self-switching transistors (SSTs) based on InGaAs/InP heterojunction. Our simulation is based on the solution of Poisson and Schrodinger equations self-consistently by using Finite Element Method (FEM). By using this method, electrical characteristics of device, such as (Formula presented.) ratio, subthreshold swing, and intrinsic gate-delay time are investigated. Also, the effects of geometrical variations on the electrical parameters of SSTs are simulated. We show that appropriate design of the device allows current modulation exceeding (Formula presented.) at room temperature. © 2021 Informa UK Limited, trading... 

    Sub-threshold charge recovery circuits

    , Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 3 October 2010 through 6 October 2010, Amsterdam ; 2010 , Pages 138-144 ; 10636404 (ISSN) ; 9781424489350 (ISBN) Khatir, M ; Mohammadi, H. G ; Ejlali, A ; IEEE; IEEE Circuits and Systems Society; IEEE Computer Society; HiPEAC Compilation Architecture ; Sharif University of Technology
    2010
    Abstract
    Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the abovementioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to... 

    Design and Analysis of Low Voltage Low-power SRAM

    , Ph.D. Dissertation Sharif University of Technology Saeidi, Roghayeh (Author) ; Hajsadeghi , Khosro (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
    Abstract
    The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. One of the key strategies for reducing power consumption is reducing the supply voltage to near or below the threshold voltage of the transistor. However, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent... 

    SRAM Cell Design for Low Power Applications

    , M.Sc. Thesis Sharif University of Technology Ganji, Mona (Author) ; Haj Sadeghi, Khosrow (Supervisor)
    Abstract
    From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of... 

    A Scan Chain-Based Aging Monitoring Scheme for Detection of Recycled Chips

    , M.Sc. Thesis Sharif University of Technology Ostovar, Atanaz (Author) ; Hesabi, Shahin (Supervisor)
    Abstract
    Today's latest technology integrated circuits are manufactured for a wide range of applications. With the constant increase in the usage rate of integrated circuits, designing a high reliable system is of utmost importance. The avoidance of counterfeit components is a major challenge of hardware security and trust. Counterfeit components cause lower performance and reduced life span. They are of great concern to the manufacturers and consumers of electronic systems, impacting the security and reliability of these systems. If these parts end up in critical applications like medical systems, satellites, aerospace, or power plants, the results could be catastrophic. So far, there are different... 

    A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM

    , Article Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013 ; 2013 , Pages 104-107 ; 9781467360388 (ISBN) Zamani, M ; Hassanzadeh, S ; Hajsadeghi, K ; Saeidi, R ; Sharif University of Technology
    Abstract
    The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense... 

    GNRFET with superlattice source, channel, and drain: SLSCD-GNRFET

    , Article Physica E: Low-Dimensional Systems and Nanostructures ; Volume 131 , 2021 ; 13869477 (ISSN) Behtoee, B ; Faez, R ; Shahhoseini, A ; Moravvej Farshi, M. K ; Sharif University of Technology
    Elsevier B.V  2021
    Abstract
    We are proposing a next-generation graphene nanoribbon field-effect transistor (GNRFET) with superlattice source, channel, and drain (SLSCD-GNRFET), with significantly improved switching performance. The presence of superlattice in each region is for energy filtering. The simulation results indicate that the addition of an appropriate superlattice in the channel region, it reduces the subthreshold swing. Also, using proper superlattice in the drain region leads to an increase of more than a decade in the ION/IOFF ratio by intensely reducing the OFF-current. These improvements make the proposed transistor potentially suitable for the next-generation logical digital applications. Comparison of... 

    Analysis and simulation of asymmetrical nanoscale self-switching transistor

    , Article International Journal of Modelling and Simulation ; Volume 42, Issue 5 , 2022 , Pages 775-781 ; 02286203 (ISSN) Horri, A ; Faez, R ; Sharif University of Technology
    Taylor and Francis Ltd  2022
    Abstract
    In this paper, we present a computational study on the electrical behaviour of self-switching transistors (SSTs) based on InGaAs/InP heterojunction. Our simulation is based on the solution of Poisson and Schrodinger equations self-consistently by using Finite Element Method (FEM). By using this method, electrical characteristics of device, such as (Formula presented.) ratio, subthreshold swing, and intrinsic gate-delay time are investigated. Also, the effects of geometrical variations on the electrical parameters of SSTs are simulated. We show that appropriate design of the device allows current modulation exceeding (Formula presented.) at room temperature. © 2021 Informa UK Limited, trading... 

    Statistical analysis of read static noise margin for near/sub-threshold SRAM cell

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, Issue. 12 , November , 2014 , pp. 3386-3393 ; ISSN: 15498328 Saeidi, R ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    A fast statistical method for the analysis of the Read SNM of a 6 T SRAM cell in near/subthreshold region is proposed. The method is based on the nonlinear behavior of the cell. DIBL and body effects are thoroughly considered in the derivation of an accurate closed form solution for the Read Static Noise Margin (SNM) of the near/subthreshold SRAM cell. This method uses the state space equation to derive the Read SNM of the cell as a function of threshold voltage of cell transistors. This function shows the dependency of the Read SNM on sizing, VDD, temperature, and threshold voltage variations. It provides a fast reliability analysis for a cell array of a given size and a supply voltage. It... 

    A subthreshold symmetric SRAM cell with high read stability

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Vol. 61, issue. 1 , Jan , 2014 , p. 26-30 ; 15497747 Saeidi, R ; Sharifkhani, M ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    This brief introduces a differential eight-transistor static random access memory (SRAM) cell for subthreshold SRAM applications. The symmetric topology offers a smaller area overhead compared with other symmetric cells for the same stability in the read operation. Two transistors isolate the cell storage nodes from the read operation path to maintain the data stability of the cell. This topology improves the data stability at the expense of read operation delay. Thorough postlayout Monte Carlo worst corner simulations in 45-nm CMOS technology are conducted. The proposed cell operates down to 0.35 V with a read noise margin of 74 mV and a write noise margin of 92 mV. Under this condition,... 

    A comparative study of NEGF and DDMS models in the GAA silicon nanowire transistor

    , Article International Journal of Electronics ; Volume 99, Issue 9 , 2012 , Pages 1299-1307 ; 00207217 (ISSN) Hosseini, R ; Fathipour, M ; Faez, R ; Sharif University of Technology
    Abstract
    In this article, we have used quantum and semiclassical models to analyse the electrical characteristics of gate all around silicon nanowire transistor (GAA SNWT). A quantum mechanical transport approach based on non-equilibrium Green's function (NEGF) method with the use of mode space approach in the frame work of effective mass theory has been employed for this analysis. Semiclassical drift diffusion mode space (DDMS) approach has also been used for the simulation of GAA SNWT. We have studied the short-channel effects on the performance of GAA SNWT and evaluated the variation of the threshold voltage, the subthreshold slope (SS), the leakage current and the drain-induced barrier lowering... 

    A new UWB pulse generator for narrowband interference avoidance

    , Article Proceedings of the Mediterranean Electrotechnical Conference - MELECON, 25 April 2010 through 28 April 2010 ; April , 2010 , Pages 759-763 ; 9781424457953 (ISBN) Mir Moghtadaei, V ; Jalili, A ; Fotowat Ahmady, A ; Nezhad, A.Z ; Hedayati, H ; Sharif University of Technology
    2010
    Abstract
    In this paper a new IR-UWB pulse generator circuit is proposed which is capable of solving the coexistence problem of narrowband and ultra wideband communication systems. This is done by creating a notch in the PSD of the generated UWB signal and adjusting its center frequency at the frequency of the narrowband interference. Using a triangular pulse generator, a triangular signal is generated and applied to the proposed circuit which consists of three main function blocks including quadratic, exponential and differentiator circuits. A differential pair MOS transistors in sub threshold region is utilized in order to realize the exponential block. The circuit is designed using a 0.18-μm RF... 

    Analysis and design of power harvesting circuits for ultra-low power applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 64, Issue 2 , 2017 , Pages 471-479 ; 15498328 (ISSN) Razavi Haeri, A. A ; Karkani, M. G ; Sharifkhani, M ; Kamarei, M ; Fotowat Ahmady, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    This paper presents an analytical model for power harvester circuits used in Ultra-low power applications. Assuming that the MOS devices of the circuit fully operate in the Sub-threshold regime in both forward and reverse regions, closed-form equations for important properties of the rectifier circuit such as output voltage, efficiency and input resistance are derived. The model includes the effect of the compensation voltage on the circuit behavior. There is a good agreement between the simulation results and the model. In addition, the contour plots needed to simultaneously optimize the matching network and the rectifier circuit are derived by the resulting equations. A 50-Stage rectifier... 

    Using superlattice structure in the source of GNRFET to improve its switching performance

    , Article IEEE Transactions on Electron Devices ; Volume 67, Issue 3 , 2020 , Pages 1334-1339 Behtoee, B ; Faez, R ; Shahhoseini, A ; Moravvej Farshi, M. K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Our aim is to improve the switching performance of the graphene nanoribbon field-effect transistors (GNRFETs), exploiting the concept of energy filtering. Within the proposed scheme, a superlattice (SL) structure is used in the source of the transistor for filtering high-energy electron tail by engineering the density of states (DOS). According to simulation results, this can significantly decrease the OFF-current and the subthreshold swing (SS). A comparison of the proposed device with a conventional GNRFET and a graphene nanoribbon (GNR) tunneling field-effect transistor (GNRTFET) demonstrates a significant improvement. Therefore, a typical SL-GNRFET can reduce the average and the minimum... 

    Joint mapping of mobility and trap density in colloidal quantum dot solids

    , Article ACS Nano ; Volume 7, Issue 7 , 2013 , Pages 5757-5762 ; 19360851 (ISSN) Stadler, P ; Sutherland, B. R ; Ren, Y ; Ning, Z ; Simchi, A ; Thon, S. M ; Hoogland, S ; Sargent, E. H ; Sharif University of Technology
    2013
    Abstract
    Field-effect transistors have been widely used to study electronic transport and doping in colloidal quantum dot solids to great effect. However, the full power of these devices to elucidate the electronic structure of materials has yet to be harnessed. Here, we deploy nanodielectric field-effect transistors to map the energy landscape within the band gap of a colloidal quantum dot solid. We exploit the self-limiting nature of the potentiostatic anodization growth mode to produce the thinnest usable gate dielectric, subject to our voltage breakdown requirements defined by the Fermi sweep range of interest. Lead sulfide colloidal quantum dots are applied as the active region and are treated... 

    Accurate estimation of leakage power variability in sub-micrometer CMOS circuits

    , Article Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012 ; 2012 , Pages 18-25 ; 9780769547985 (ISBN) Assare, O ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
    2012
    Abstract
    Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical...