Sharif Digital Repository

A new level converter for use in dual voltage SOI digital circuits is presented. The technique which uses the idea of keeper transistors, consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations  

A high speed, high resolution switched-current sample and hold (SI S/H) based on a new class AB transconductance stage is presented. Simulations performed on the SI S/H in standard 0.18um CMOS technology with 1.5v supply voltage indicate low power dissipation, high sampling speed and high SNR. © 2006 IEEE  

An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE  

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

An ultra-efficient switching method for successive approximation register ADCs is proposed. In this method, the input signals are sampled in a special fashion to reduce the switching energy. Owing to the sampling method, only one reference voltage (Vq=Vref/4) is required to implement the switching steps. Therefore, in addition to reduction in the switching energy (due to the lower supply voltage), the precision of the DAC is improved. The proposed method reduces the switching energy and area by 99.41 and 50%, respectively, compared with the conventional method. © 2016 The Institution of Engineering and Technology  

A new level converter for use in dual voltage SOI digital circuits is presented. This technique uses the idea of keeper transistors, and consumes less power compared to the traditional methods. The effects of load capacitance on the circuit are studied by extensive simulations. © 2006 IEEE  

A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE  

This paper presents a zero-voltage switching current mode sample and hold(S/H) circuit. The proposed S/H has 12 bit linearity at 180MHz sampling rate for 1.5v supply voltage. The S/H circuit is designed for 0.18μm CMOS technology  

A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power  

This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is... 

A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

On-chip accurate clock references are one of the essential building blocks in fully integrated Systems-On-Chips (SOC). In this paper, a low phase noise, temperature and supply voltage independent clock reference is presented. It provides the reference frequency for a biomedical implantable system. The simulated phase noise at 100 KHz offset from 2MHz carrier is 113dBc/Hz. Simulations show the frequency remains within 0.34% of the nominal oscillation frequency in the operating voltage range of 1.7 - 1.9 V without any calibration and its change in the temperature range of 20-to100C is 0.5%. The circuit consumes 77W and is designed in a 0.18m technology with 1.8V supply voltage  

This paper used a 4-level frequency shift keying (4-FSK) modulation scheme to enhance the density of wireless data transfer from implantable biomedical microsystems to the outside world. Modeling and simulation of the wireless channel for 4-FSK modulation in the case of a neural recording implant has been done. To realize the 4-FSK scheme, the modulator and demodulator circuits are proposed, designed and simulated in a 0.18-μm CMOS process, and in the 174-216 MHz frequency band at a data rate of 13.5 Mbps. Operated using a 1.8 V supply voltage, the modulator circuit consumes a power of 7.8 μW  

Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

A new technique for improving the performance of low-voltage folding ADC's by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input-output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power... 

Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

The design of a Gm-C filter for High-Frequency applications is described in this paper. A low-pass, sixth-order elliptic Gm-C filter based on the new biquadratic architecture in 0.18 um CMOS process is designed with the proper dynamic rang. A simple structure of the high Q biquadratic filter is used to enhance the linearity and tunability of the filter. The cut off frequency of this filter is 33 MHz. It has a THD of -45 dB for 0.2 Vpp, 8 MHz signal. The complete filter including on-chip tuning circuit consumes only 0.8mA with 1.8 V single supply voltage. ©2006 IEEE  

An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first...