Sharif Digital Repository

To get a more accurate model for the simulation of single electron transistors (SETs), we propose a new macro-model that includes an electron tunneling time calculation. In our proposed model, we have modified the previous models and have applied some basic corrections to the formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for a high-speed simulation and observed that the simulation results obtained from our model match more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more accurate... 

In this paper a new technique called switched-resistor is used as an alternative to switched-capacitor circuits in a low-voltage low-power high-speed A/D converter. Simulation results for an 8-bit 150MS/s pipeline ADC are presented. This converter consumes 20mW from a 1.8V supply and provides an ENOB of 7.5bit. © 2007 IEEE  

Drawing an accurate relationship between settling time and the power consumption of the amplifier is a challenging problem in Switch Capacitor circuits especially when it includes non-linear effects. In this paper, a new method for the estimation of this relationship including both non-linear settling as a result of slew-rate and small signal settling in the 3 rd order amplifier is proposed. The results show that the proposed settling time estimation is more accurate than other conventional methods when it is compared with the circuit level simulations. The proposed method has error smaller than 10% for the third order OpAmp in estimating settling error. This is about two times more accurate... 

A new second order sigma delta modulator with the reduced number of op-amps, to decrease static power consumption and area, is presented for voice band applications such as codecs. This switched capacitor modulator uses reused capacitor technique to reduce the input thermal noise and circuit area. It improves the DR of modulator by almost 0.5 bit. The modulator shows 87 dB DR for voice band while consuming 125 μW from a 2.5 V supply. © 2003 IEEE  

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed... 

To get a more accurate model for simulation of single electron transistors (SETs), we have proposed a new macromodel that includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition, we have added a switched capacitor circuit, as a quantizer, to calculate the electron tunneling time. We used HSPICE for high-speed simulation and observed that the simulation results obtained from our model matched more closely with that of SIMON 2.0. We also could evaluate the time of electron tunneling through the barrier by using the quantizer. Clearly, our macro-model gives more... 

Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response  

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

A novel class AB architecture for single stage multipath differential amplifier is presented. The proposed amplifier combines the flipped voltage follower(FVF) for differential input and the nonlinear current mirror for active load. Applying these techniques to telescopic-cascode amplifier increases the unity-gain bandwidth, the DC gain and the slew rate while the same power consumption as the conventional telescopic cascade is achieved  

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the...