Sharif Digital Repository

In parallel with enhancements in the technology of integrated circuits, transistors are implemented in silicon. Though the price is reduced; design is more complicated, which create the efficiency and power consumption. The reason why modern GDI-based circuit is the focus of attention is that in designing digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of logic circuit can bring about reduction of power consumption, propagation delay and decrease circuit space. GDI-based integrated circuit resembles MOSFET transistors but have fewer transistors and higher performance capability. This study addresses two main areas which are Studying and... 

In Minimally Invasive Surgery (MIS) the operation is performed through introducing surgery instruments, graspers, scissor into the body. In the present work, a novel smart grasper is presented in which the surgeon can virtually acquire a feeling of force/momentum experienced by the organ/tissue. The smart grasper uses piezoelectric sensors bonded at desired locations to detect the applied force/momentum by surgeon and to measure the transmitted response to the tissue/organ. © 2009 IEEE  

Sectionalizing switches play a crucial role in enhancing service reliability to the end users of distribution networks. However, they might encounter failures, thereby causing interruptions in the networks. The existing switch placement models consider only the pros of switches in improving service reliability, while they fail to deem switches cons in possible failures and thus increasing system interruptions. This letter intends to show the importance of switch failure in the switch placement problem and the extent to which switch failure alters the switches allocation in a network. To do so, we develop a novel model based on mixed integer programming format to integrate the impacts of... 

Sectionalizing switches play a crucial role in enhancing service reliability to the end users of distribution networks. However, they might encounter failures, thereby causing interruptions in the networks. The existing switch placement models consider only the pros of switches in improving service reliability, while they fail to deem switches cons in possible failures and thus increasing system interruptions. This letter intends to show the importance of switch failure in the switch placement problem and the extent to which switch failure alters the switches allocation in a network. To do so, we develop a novel model based on mixed integer programming format to integrate the impacts of... 

This paper presents a zero-voltage switching current mode sample and hold(S/H) circuit. The proposed S/H has 12 bit linearity at 180MHz sampling rate for 1.5v supply voltage. The S/H circuit is designed for 0.18μm CMOS technology  

A new second order sigma delta modulator with the reduced number of op-amps, to decrease static power consumption and area, is presented for voice band applications such as codecs. This switched capacitor modulator uses reused capacitor technique to reduce the input thermal noise and circuit area. It improves the DR of modulator by almost 0.5 bit. The modulator shows 87 dB DR for voice band while consuming 125 μW from a 2.5 V supply. © 2003 IEEE  

In this paper, we aim to improve the performance and power metrics of packet-switched network-on-chips (NoCs) and benefits from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The proposed method sets up the virtual point-to-point (VIP) connections over one virtual channel (which bypasses the entire router pipeline) at each physical channel of the NoC. We present two schemes for constructing such VIP circuits. In the first scheme, the circuits are constructed for an application based on its task-graph at design time. The second scheme addresses constructing the connections at run-time using a light-weight... 

Abstract Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time... 

Thermal noise is one of the most important limiting factors on the performance of switched-capacitor (SC) circuit due to the aliasing effect of wide-band thermal noise. In this paper a new simple method for estimating the effect of thermal noise is presented. In the proposed technique only the discrete sampled noise is considered. HSPICE simulator and analytical analysis are used to estimate the sampled noise specification on each clock state. Next, using difference equations of the circuit, time domain simulation is done by MATLAB. Based on this method, a SC integrator is analyzed and results compared to the measured noise response  

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation... 

In this paper, we aim to improve the performance and power metrics of packet-switched network-on-chips (NoCs) and benefits from the scalability and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The proposed method sets up the virtual point-to-point (VIP) connections over one virtual channel (which bypasses the entire router pipeline) at each physical channel of the NoC. We present two schemes for constructing such VIP circuits. In the first scheme, the circuits are constructed for an application based on its task-graph at design time. The second scheme addresses constructing the connections at run-time using a light-weight... 

Sigma-Delta modulator ADCs used in signal processing applications usually, are implemented by switched-capacitor (SC) circuits and CMOS transmission gates due to its simplicity for implementation. Channel charge injection (CCI) and clock feed-through (CFT) are two major non-ideal effects existing in TG switches and SC integrators reducing modulator total SNR, its linearity and its total gain. This paper presents a precise model for SC integrator including CCI and CFT non-ideal effects in MATLAB SIMULINK environment which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) Sigma-Delta modulators. Evaluation and validation of extracted models were... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

Sectionalizing switches play a crucial role in enhancing service reliability to the end users of distribution networks. However, they might encounter failures, thereby causing interruptions in the networks. The existing switch placement models consider only the pros of switches in improving service reliability, while they fail to deem switches cons in possible failures and thus increasing system interruptions. This study intends to show the importance of switch failure in the switch placement problem and the extent to which switch failure alters the switches allocation in a network. To do so, we develop a novel model based on mixed integer programming format to integrate the impacts of... 

The necklace hypercube has recently been introduced as an attractive alternative to the well-known hypercube. Previous research on this network topology has mainly focused on topological properties, VLSI and algorithmic aspects of this network. Several analytical models have been proposed in the literature for different interconnection networks, as the most cost-effective tools to evaluate the performance merits of such systems. This paper proposes an analytical performance model to predict message latency in wormhole-switched necklace hypercube interconnection networks with fully adaptive routing. The analysis focuses on a fully adaptive routing algorithm which has been shown to be the most... 

Irregular topologies are desirable network structures for building scalable cluster systems and very recently they have also been employed in SoC (system-on-chip) design. Many analytical models have been proposed in the literature to evaluate the performance of networks with different topologies such as hypercube, torus, mesh, hypermesh, Cartesian product networks, star graph, and k-ary n-cube; however, to the best of our knowledge, no mathematical model has been presented for irregular networks. Therefore, as an effort to fill this gap, this paper presents a comprehensive mathematical model for fully adaptive routing in wormhole-switched irregular networks. Moreover, since our approach... 

This paper introduces "switched-resistor" circuits as a new family of current-mode sampled-data circuits with improved accuracy and linearity. Advantages of the switched-resistor circuits for high-speed and low-voltage applications are demonstrated. A switched-resistor biquad band-pass filter with a quality factor of 10 and clock frequency of 100 MHz, fabricated in a 0.18 μ m CMOS process, is also presented. The filter consumes 9 mW from 1.8 V supply. © 2008 Elsevier GmbH. All rights reserved  

This paper presents a simulation-based study of the stuck-open fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting stuck-open faults in these logic families. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE  

The state-space averaging applied to switched networks generally results in nonlinear systems. It is common to perform a small signal linearization about an operating point to obtain a linear system. When the variations in signals are large, e.g., in PFC rectifiers, the small signal approximation produces results that are susceptible to instability problems. In this paper a class of piecewise linear models merged by fuzzy system are introduced for PWM converters. The necessary and sufficient and conditions for stability of fuzzy models using fuzzy state-feedback controllers are given. The results obtained are illustrated with a buck-boost converter. The simulation and experimental results... 

The Cúk converter operating in discontinuous capacitor voltage mode (DCVM) inherently benefits from PFC features as unity power factor can be achieved by using a constant duty cycle and switching frequency. In this paper, the switch network modeling technique is applied to the Cúk converter operating in DCVM in order to develop its small-signal model under the assumption that it is fed by a dc voltage source. Afterwards, the model is extended to derive the small-signal behavior of the converter while operating as a PFC converter. The validity of the proposed model is confirmed by both simulation and experimental results