Sharif Digital Repository

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson... 

In this paper, a silicon-on-insulator (SOI) p-n-p-n tunneling field-effect transistor (TFET) with a silicon doped hafnium oxide (Si:HfO2) ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band-to-band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3) and strontium bismuth tantalate (SrBi2Ta2O9) provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling... 

Memristor devices have attracted tremendous interest due to different applications ranging from nonvolatile data storage to neuromorphic computing units. Exploring the role of surface roughness of the bottom electrode (BE)/active layer interface provides useful guidelines for the optimization of the memristor switching performance. This study focuses on the effect of surface roughness of the BE electrode on the switching characteristics of Au/TiO2/Au three-layer memristor devices. An optimized wet-etching treatment condition was found to modify the surface roughness of the Au BE where the measurement results indicate that the roughness of the Au BE is affected by both duration time and... 

In this paper, we propose a packet-switched network-on-chip (NoC) architecture which can provide a number of low-power, low-latency virtual point-to-point connections for communication flows. The work aims to improve the power and performance metrics of packet-switched NoC architectures and benefits from the power and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The virtual point-to-point connections are set up by bypassing the entire router pipeline stages of the intermediate nodes. This work addresses constructing the virtual point-to-point connections at run-time using a light-weight setup network. It involves monitoring... 

Our aim is to improve the switching performance of the graphene nanoribbon field-effect transistors (GNRFETs), exploiting the concept of energy filtering. Within the proposed scheme, a superlattice (SL) structure is used in the source of the transistor for filtering high-energy electron tail by engineering the density of states (DOS). According to simulation results, this can significantly decrease the OFF-current and the subthreshold swing (SS). A comparison of the proposed device with a conventional GNRFET and a graphene nanoribbon (GNR) tunneling field-effect transistor (GNRTFET) demonstrates a significant improvement. Therefore, a typical SL-GNRFET can reduce the average and the minimum...