Sharif Digital Repository

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. In this work, we investigate adding heterogeneous hot redundancy (i.e., the architecture of redundant hot cores is diferent from the baseline cores) to improve the cost and performance of multicore single-instruction, multiple-thread (SIMT) architectures. We propose to utilize x86 out of order (OoO) cores as redundancy in SIMT processors. In this case, dice with unused functional redundancies can beneit from two types of processing cores (OoO and SM)  

In this paper, we integrate an assertion-based verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification. In this direction a system-level assertion language is defined. The system-level assertions can be used to monitor the current state of system or flow of transactions. These assertions are automatically converted to "monitor hardware" or "monitor software" during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertions, and hence, can be reused to verify the... 

Due to wireless communication’s rapid growth, the need for low power integrated transceivers is increasing. The receiver power is a major limiting factor, and the radio frequency (RF) front-end is often its significant power consuming part. Therefore, system-level design in which the overall specifications are distributed among RF front-end building blocks such that the minimum total power is consumed is crucial. A complete system-level design method for a low power RF front-end is presented in this paper. For this purpose, the performance of each block is modeled by its current and overdrive voltage. An analytical associated with a search-based optimization technique is employed to derive... 

In this paper, we enhance previously suggested vulnerability estimation techniques by presenting a detailed modeling technique based on Input-to-Output Masking (IOM). Moreover we use our model to compute the System-level Vulnerability Factor (SVF) for data-path components in a highperformance processor. As we show, recent suggested estimation techniques overlook the issue of error masking, mainly focusing on time periods in which an error could potentially propagate in the system. In this work we show that this is incomplete as it ignores the masking impact. Our results show that including the IOM factor can significantly affect the system-level vulnerability for data-path components. As a... 

In this paper, we present an assertion-based verification methodology for system-level design. Transactionlevel concepts are integrated with an assertion language to introduce a useful, effective and familiar assertion description language. Our assertion verification language is capable of specifying system-level assertions for validating performance as well as functional properties. Proper-ties can be verified using offline simulation trace analysis. C++ trace checkers are automatically generated to validate particular simulation runs or to analyze their performance characteristic(s). Using a JPEG decoder as a case study, we demonstrate that the assertion-based verification is highly useful... 

In this paper we integrate a verification methodology with our object-oriented system-level synthesis methodology to address the problem of HW/SW co-verification after system synthesis. We have defined a set of system-level assertions. These assertions are automatically converted to monitor hardware or monitor software during the system-level synthesis process depending on their type and also synthesis style of their corresponding functions. The synthesized assertions are functionally equivalent to their original system-level assertion, and hence, can be used to verify the system after HW/SW synthesis. This way, not only system-level assertions are reused in lower-levels of abstraction, but... 

IP core reuse is popular for designing and implementing complex systems, because reuse of already provided blocks decreases design time and so diminishes productivity gap. Moreover, as system-level design methodologies and tools emerge for embedded system design, it is useful to have a shift from Register Transfer Level to system-level models for IP cores employed for implementation of hardware parts of the system. In this paper, we propose a C++ model for hardware IP cores that can be adopted as a standard for delivering IPs at a high level of abstraction, suitable for object-oriented system-level design methodologies. Next, we extend our system-level synthesizer in order to integrate IP... 

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

With continuous technology downscaling, the rate of radiation induced soft errors is rapidly increasing. Fast and accurate soft error vulnerability analysis in early design stages plays an important role in cost-effective reliability improvement. However, existing solutions are suitable for either regular (a.k.a address-based such as memory hierarchy) or irregular (random logic such as functional units and control logic) structures, failing to provide an accurate system-level analysis. In this paper, we propose a hybrid approach integrating architecture-level and logic-level techniques to accurately estimate the vulnerability of all regular and irregular structures within a microprocessor.... 

Delivery of the Smart Grid is a topic of considerable interest within the power industry in general, and the IEEE specifically. This paper presents the smart grid landscape as seen by the IEEE Dielectrics and Electrical Insulation Society (DEIS) Technical Committee on Smart Grids. We define the various facets of smart grid technology, and present an examination of the impacts on dielectrics within power assets. Based on the trajectory of current research in the field, we identify the implications for asset owners and operators at both the device level and the systems level. The paper concludes by identifying areas of dielectrics and insulation research required to fully realize the smart... 

As manufacturing processes scale to smaller feature sizes and processors become more complex, it is becoming challenging to have fabricated devices that operate according to their speciication in the irst place: yield losses are mounting [3]. © 2017 ACM  

Rhythmic activities such as swimming stroke in the human body are learnable through conscious trainings. Inspiringly, the main objective of this study is to develop a control framework to reproduce the described functionality in the imitating robots. To do so, a two layer supervisory controller is proposed. The high-level controller, which acts as the conscious controller during trainings, is a supervisory dynamic-based controller and uses all system sensory data to generate stable rhythmic movements. On the other hand, the low-level controller in this structure is a distributed trajectory-based controller network. Each node in this network is an oscillatory dynamical system which has the... 

In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE  

In this paper, we present a JPEG decoder implemented in our ODYSSEY design methodology. We start with an object-oriented JPEG decoder model. The total operation from modeling to implementation is done automatically by our EDA tool-set in about 10 hours. The resultant system is a JPEG decoder ASIP whose hardware part is implemented on FPGA logic blocks and software part runs on a MicroBlaze processor. This ASIP can be extended by software routines to implement the motion JPEG or MPEG2 decoding algorithms. We implemented our system on ML402 FPGA-based prototype board. Experimental results show that our ASIP implementation is comparable to other approaches while our approach enables quick and... 

Over the past few years, radiation-induced transient errors, also referred to as soft errors, have been a severe threat to the data integrity of high-end and mainstream processors. Recent studies show that cache memories are among the most vulnerable components to soft errors within high-performance processors. Accurate modeling of the Vulnerability Factor (VF) is an essential step towards developing cost-effective protection techniques for cache memory. Although Fault Injection (FI) techniques can provide relatively accurate VF estimations they are often very time consuming. To overcome the limitation, recent analytical models were proposed to compute the cache VF in a timely fashion. In... 

The present study investigates the possibility of using a small hydropower/PV hybrid power system for low-cost electricity production which can satisfy the energy load requirements of a typical rural-urban area. In this context, the optimal dimensions to improve the technical and economical performances of the hybrid system are determined according to the load energy requirements and the solar and hydro resources data using linear programming. The application of the model is demonstrated using a case study of a rural-urban area in Mazandaran province, Iran. Two scenarios were considered for optimizing the system components. In the first scenario, a stand-alone hybrid small hydropower/PV...