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Investigating the effects of process variations and system workloads on endurance of non-volatile caches
, Article 13th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, 23 October 2017 through 25 October 2017 ; Volume 2018-January , 2018 , Pages 1-6 ; 9781538603628 (ISBN) ; Farbeh, H ; Miremadi, S. G ; Cadence; IEEE; IEEE Computer Society; IEEE Fault-Tolerant Computing Technical Committee; IEEE Test Technology Technical Council (TTTC) ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
With the development of Non-Volatile Memory (NVM) technologies in recent years, several studies suggest using them as an alternative for SRAMs in on-chip caches. One of the main challenges in replacing SRAMs with NVMs is limited endurance of NVMs (i.e. the maximum allowed number of write operations in an NVM cell). The endurance of NVM caches is directly affected not only by workload behaviors, but also by process variations (PVs). Several studies characterized the endurance of NVM caches but they do not consider the simultaneous effects of the PVs and the workloads. In this paper, we propose a high-level framework to investigate the endurance of NVM caches affected by the per-cell endurance...