Loading...
Search for: target-application
0.005 seconds

    Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology

    , Article Microprocessors and Microsystems ; April , 2016 ; 01419331 (ISSN) Mehrvarzy, P ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier  2016
    Abstract
    Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

    Power- and performance-efficient cluster-based network-on-chip with reconfigurable topology

    , Article Microprocessors and Microsystems ; Volume 46 , 2016 , Pages 122-135 ; 01419331 (ISSN) Mehrvarzy, P ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier B.V  2016
    Abstract
    Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

    A cache-assisted scratchpad memory for multiple-bit-error correction

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 24, Issue 11 , 2016 , Pages 3296-3309 ; 10638210 (ISSN) Farbeh, H ; Sadat Mirzadeh, N ; Farhady Ghalaty, N ; Miremadi, S. G ; Fazeli, M ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache memory to provide a replica for SPM lines. Using cache memory, CADS is able to guarantee a full duplication of all SPM lines. We also further enhance the proposed scheme by presenting buffered CADS (BCADS) that significantly improves the CADS energy efficiency. BCADS is compared with two well-known...