Sharif Digital Repository

In this paper, a new method to achieve very small current reference levels on integrated circuits with immunity to temperature variations using peaking current source with MOSFETs operating in subthreshold region is proposed. By adding a source degeneration resistor to the conventional peaking current source architecture, a zero temperature coefficient current can be generated. The proposed low-power circuit operating in the weak inversion region is designed, simulated, and fabricated in a 0.18-μm standard CMOS process. Measurement results verify the circuit operation with about 5% variation over the span of -40° C to +100° C (industrial temperature grade). The supplied current is designed... 

In this brief, modifications to the peaking current reference with MOS transistors operating in the subthreshold and the strong inversion region has been proposed by means of which very small currents with immunity to temperature variations on a chip can be obtained. Temperature compensation can be done by adding a source degeneration resistor to the conventional peaking current source structure. Design examples are provided for both weak and strong inversion operations with output currents of 1.5 μA and 40 μ A with less than 4% and 10% variation over the span of-40 °C to +100 °C, respectively. A prototype of the circuit operating in the weak and strong inversion region is designed,... 

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and... 

Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is... 

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a 0.18μm CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst...