Sharif Digital Repository

In this paper we present an analytical model to analyze the influence of deep level traps on the static and dynamic responses of transistor laser (TL). Our analysis is based on analytically solving the continuity equation and rate equations including the effect of the deep level trap (DLT), which incorporates the virtual states as a conversion mechanism. The results of simulation show that the main characteristics of laser such as threshold current, quantum efficiency, output power, and modulation bandwidth are affected by total density of traps in the active region  

In this paper, we present an analytical model to analyze the influence of deep level traps on the static and dynamic responses of transistor laser (TL). Our analyze is based on analytically solving the continuity equation and rate equations including the effect of the deep level trap (DLT), which incorporate the virtual states as a conversion mechanism. The results of simulation show that the main characteristics of laser such as threshold current, quantum efficiency, output power, and modulation bandwidth are affected by total density of traps in the active region  

The comprehensive optical-electrical-gain-thermal self-consistent model of the 1.55 μm AlGaInAs Photonic Crystal vertical cavity surface emitting diode lasers (PhC VCSELs) with buried tunnel junction (BTJ) has been applied to optimize its threshold characteristics. It shows that, for 5 μm devices, the room temperature (RT) threshold current equal to only 0.59 mA and maximum operating temperature equal to as much as 380 K. Results suggest that, the 5 μm AlGaInAs PhC VCSELs seem to be the most optimal ones for light sources in high performance optical communication systems  

In the present work, a new structure of vertical cavity surface emitting laser (VCSEL) is designed and simulated. In this structure, InGaAsP is used as the active region which is sandwiched between GaAs/AlGaAs distributed bragg mirror at the top of structure and GaAs/AlAs distributed bragg mirror at the bottom. In this work, the hole etching depth was continued down to the top of lower spacer layer while in the previous work the hole etching depth was only down to top of the upper spacer. In this way, the threshold current decrement of 76.52% and increment the power by 28% from 5mW to 6.4mW at bias current of 9mA was achieved. In this paper, device characteristics such as light power versus...