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    A wide dynamic range low power 2× time amplifier using current subtraction scheme

    , Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 462-465 ; 02714310 (ISSN); 9781479953400 (ISBN) Molaei, H ; Khorami, A ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

    A low power high resolution time to digital converter for ADPLL application

    , Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) Molaei, H ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

    Time to Digital Converters for ADPLL Applications

    , Ph.D. Dissertation Sharif University of Technology Molaei, Hasan (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations.... 

    A 5.3ps 8b Time to digital converter using a new gain-reconfigurable time amplifier

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN) Molaei, H ; Hajsadeghi, K. H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

    A 5.3-ps, 8-b time to digital converter using a new gain-reconfigurable time amplifier

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 66, Issue 3 , 2019 , Pages 352-356 ; 15497747 (ISSN) Molaei, H ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012...