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    Pipelining method for low-power and high-speed SAR ADC design

    , Article Analog Integrated Circuits and Signal Processing ; Volume 87, Issue 3 , 2016 , Pages 353-368 ; 09251030 (ISSN) Fazel, Z ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
    Springer New York LLC 
    Abstract
    A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel... 

    Compensation and Calibration of ADCs

    , M.Sc. Thesis Sharif University of Technology Khanmohammad, Hesam (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    Increasing demand for high-speed and high-resolution ADCs as much as low-power ones and on the other hand, the obstacles in the way of reaching them make calibration and compensation methods more significant for obtaining ADCs with the better specs. Among the cases which need modification, the modification of C-2C-based SAR ADCs, which can decrease the power significantly, and the modification of time-skew error of time-interleaved ADCs, which is the main and the most challenging error in this type of ADCs, could be the two of the effective ways to making the State-of-the-Art ADCs. In this project for the first time, a novel compensation method for C-2C parasitic charges is proposed which... 

    A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects

    , Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) Sariri, H ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

    Approximateml estimator for compensation of timing mismatch and jitter noise in Ti-ADCS

    , Article European Signal Processing Conference, 28 August 2016 through 2 September 2016 ; Volume 2016-November , 2016 , Pages 2360-2364 ; 22195491 (ISSN) ; 9780992862657 (ISBN) Araghi, H ; Akhaee, M. A ; Amini, A ; Sharif University of Technology
    European Signal Processing Conference, EUSIPCO  2016
    Abstract
    Time-interleaved analog to digital converters (TI-ADC) offer high sampling rates by passing the input signal through C parallel low-rate ADCs. We can achieve C-times the sampling rate of a single ADC if all the shifts between the channels are identical. In practice, however, it is not possible to avoid mismatch among shifts. Besides, the samples are also subject to jitter noise. In this paper, we propose a blind method to mitigate the joint effects of sampling jitter and shift mismatch in the TI-ADC structure. We assume the input signal to be bandlimited and incorporate the jitter via a stochastic model. Next, we derive an approximate model based on a first-order Taylor series and use an... 

    10-Bit 500-MS/s Pipelined Analog to Digital Converter

    , M.Sc. Thesis Sharif University of Technology Noormohammadi Khyarak, Mehdi (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to... 

    Design of a High Speed Time-Interleaved SAR ADC

    , M.Sc. Thesis Sharif University of Technology Ghajari, Shahaboddin (Author) ; Sharifkhani, Mohammad (Supervisor) ; Fotowat Ahmadi, Ali (Supervisor)
    Abstract
    The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be...