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    A low power 1.2 GS/s 4-bit flash ADC in 0.18 μm CMOS

    , Article Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 ; 2013 ; 9781479920969 (ISBN) Chahardori, M ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
    2013
    Abstract
    A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

    A 4-Bit, 1.6 GS/s low power flash ADC, based on offset calibration and segmentation

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 9 , 2013 , Pages 2285-2297 ; 15498328 (ISSN) Chahardori, M ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
    2013
    Abstract
    A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

    Nonisothermal two-phase modeling of the effect of linear nonuniform catalyst layer on polymer electrolyte membrane fuel cell performance

    , Article Energy Science and Engineering ; Volume 8, Issue 10 , 2020 , Pages 3575-3587 Sabzpoushan, S ; Jafari Mosleh, H ; Kavian, S ; Saffari Pour, M ; Mohammadi, O ; Aghanajafi, C ; Ahmadi, M. H ; Sharif University of Technology
    John Wiley and Sons Ltd  2020
    Abstract
    In this research, it is investigated to numerically evaluate the performance of a polymer electrolyte membrane fuel cell (PEMFC). The performance is investigated through the nonuniformity gradient loading at the catalyst layer (CL) of the considered PEMFC. Computational fluid dynamics is used to simulate a 2D domain in which a steady-state laminar compressible flow in two-phase for the PEMFC has been considered. In this case, a particular nonuniform variation inside the CL along the channel is assumed. The nonuniform gradient is created using a nonisothermal domain to predict the flooding effects on the performance of the PEMFC. The computational domain is considered as the cathode of PEMFC,...