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wireless-network-on-chip
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Design and Implementation of Decoder and Encoder for Error Detecting and Correcting Algorithms for RF Links in Networks on Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shaahin (Supervisor)
Abstract
In the upward trend of advancing technologies in chips manufacturing, utilizing Network on Chip (NOC) solutions is a sensible approach towards overcoming challenges in System on Chip (SOC). The most common form of NOC is the Wired NOC. The continuous physical size reduction of electronic circuits has led to bandwidth deficiency as well as increased temperature in various parts of these circuits. The vast advancement in chips manufacturing industry has made it possible to embed and adapt telecommunication equipment into chips, giving rise to Wireless NOC (WNOC) manufacturing. However, wireless communication increases fault rate; thereby, the system becomes more vulnerable against transient...
Design of Wired/Wireless Hybrid 3D NoC for Radio Components and 3D Digital Structure Compliance
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor)
Abstract
According to recent advancements in digital circuit technology and new constraints for digital systems, scholars have researched to find a replacement for traditional copper links that is used to connect the embedded processing elements in a chip. Optic NoCs and wireless NoCs are two promising solutions to overcome challenges in traditional NoCs.
In this thesis, an innovative 3D NoC architecture is proposed which consists of four 2D mesh-based networks and they are connected via four wireless sub-networks as backbones. It is estimated that, the proposed architecture shrinks the power consumption at least 35 percent relatively due to the gate-level simulations. Thus, a better scaling and...
In this thesis, an innovative 3D NoC architecture is proposed which consists of four 2D mesh-based networks and they are connected via four wireless sub-networks as backbones. It is estimated that, the proposed architecture shrinks the power consumption at least 35 percent relatively due to the gate-level simulations. Thus, a better scaling and...
Multi-hop communications on wireless network-on-chip using optimized phased-array antennas
, Article Computers and Electrical Engineering ; Volume 39, Issue 7 , 2013 , Pages 2068-2085 ; 00457906 (ISSN) ; Tabandeh, M ; Kaffash, S ; Raahemi, B ; Sharif University of Technology
2013
Abstract
Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC); The advantages of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the International Technology Roadmap for Semiconductors annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the...
Providing Methods for Reducing and Estimating the Power Consumption of Wireless Networks on Chip
, M.Sc. Thesis Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Rahemi, Bijan (Supervisor)
Abstract
In recent years, the possibility of building large systems on chip, called SoC is provided. By scaling the technology, designing Socs will face numerous challenges. The Noc paradigm, has resolved many of the SoC’s problems, by deploying network properties in the structures of on chip interconnections. Today, with advances in the semiconductor industry, we can implement broadband wireless antennas, which are integrated on chip. Such NoCs are called WNoC. Due to immaturity of WNoCs, there still exist big challenges, providing routing algorithm and controlling shared medium via MAV layers, for them. In this project, we will provide a routing algorithm based on tag switching, and then, after...
Fault Tolerant Routing in Wireless Network on Chip
, Ph.D. Dissertation Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Raahemi, Bijan (Co-Advisor)
Abstract
Network-on-Chip (NoC) as a promising design approach for on-chip interconnect fabrics could overcome the energy as well as synchronization challenges of the conventional interconnects in the gigascale System-on-Chips (SoC). The advantage of communication performance of traditional wired NoC will no longer be continued by the future technology scaling. Packets that travel between distant nodes of a large scale wired on-chip network significantly suffer from energy dissipation and latency due to the routing overhead at each hop. According to the ITRS annual report, the RFCMOS characteristics will be steadily improved by technology scaling. As the operating frequency of RF devices increases,...
An optimized phased-array antenna for intra-chip communications
, Article LAPC 2011 - 2011 Loughborough Antennas and Propagation Conference, 14 November 2011 through 15 November 2011 ; November , 2011 , Page(s): 1 - 4 ; 9781457710155 (ISBN) ; Tabandeh, M ; Kaffash, S ; Sharif University of Technology
2011
Abstract
The continued migration to smaller nanometer geometries brought fundamental limits to traditional on-chip hard wires performance. According to the International Technology Roadmap for Semiconductor (ITRS), feature size shrinking leads an increase in the operating frequency of RFCMOS devices. Thus, new interconnect methodologies such as radio frequency (RF) wireless can be employed on future chips projected for intra-chip wireless data communications. The size of Si integrated antenna in these frequencies will be several millimetres and the antenna length will be decrease by frequency increasing. In this paper, we have proposed an optimum radiation pattern achieved by a phased array (PA)...