Sharif Digital Repository

This paper presents a VLSI architecture of a novel softoutput K-Best MIMO detector. The proposed detector attains low computational complexity using three improvement ideas: relevant discarded paths selection, last stage on-demand expansion, and relaxed LLR computation. A deeply pipelined architecture for a soft-output MIMO detector is implemented for a 4x4 64-QAM MIMO system realizing a peak throughput of 655Mbps, while consuming 174K gates and 195mW in 0.13um CMOS. Synthesis results in 65nm CMOS show the potential to support a sustained throughput up to 2Gbps achieving the data rates envisioned by emerging IEEE 802.16m and LTE-Advanced wireless standards  

The current literature lacks the VLSI realization of hig-horder multiple-input-multiple-output (MIMO) detectors in the complex domain, which finds applications in advanced wireless standards such as WiMAX and Long Term Evolution (LTE) systems. In this paper, a novel modified complex K-Best algorithm and its VLSI implementation for a 4 ×4, 64QAM complex MIMO detector are proposed. The main contributions of this paper are the modified hard-output complex K-Best algorithm as well as its efficient architecture, which is well-suited for a pipelined VLSI implementation. By using an efficient fast multiplier and applying both fine-grain pipelining and coarse-grain pipelining to the architecture of...