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Reducing Power Consumption in NoCs Through Adaptive Data Encoding

Taassori, Meysam | 2009

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 39141 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power consumed in the integrated circuits, and this fraction is expected to grow in future. One way to reduce the power consumption of global interconnects is to reduce the switching activity by means of coding methods. These encoding schemes are called low power encoding algorithms. In this thesis inserting the low power encoding into the transport layer of NoC infrastructures is evaluated and the effect of properties of mesh NoCs on the effectiveness of these encoding schemes are studied. Two criteria for making these encoding schemes adaptive based on the system conditions are proposed. These criteria improve the effectiveness of these methods. According to the trend of technology and shrinking the feature size, the coupling capacitances exceed the self-capacitance on the wire. Therefore, encoding algorithms, which ignore the coupling capacitances and try to minimize the self-transition, cannot be effective in DSM technologies. A new encoding scheme is proposed based on the bus invert algorithm that decreases not only transition activity on coupling capacitances, but also the self-transition on links. Finally, a solution is proposed to adapt the bus invert method and its derivatives for NoC infrastructures
  9. Keywords:
  10. Network-on-Chip (NOC) ; Power Consumption ; Efficiency ; Data Encoding

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