Clock and Data Recovery Circuit For High Speed Serial Communication

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Mousavi, Hassan | 2010

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 40606 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Hajsadeghi, Khosroo
Abstract:
In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies
Keywords:
Phase Locked Loop (PLL) ; Phase Detector ; Voltage Controlled Oscillator ; Clock and Data Recovery Circuit

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