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VLSI Architecture for MIMO Detectors in the Complex Domain

Mahdavi, Mojtaba | 2010

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 41000 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Vosoughi Vahdat, Bijan; Shabany, Mahdi
  7. Abstract:
  8. The implementation of high-order multiple-input multiple-output (MIMO) detectors in complex domain, which finds applications in advanced wireless standards such as WiMAX and Long Term Evolution (LTE) systems, has always been a challenge in the literature. To address this challenge, two novel detection algorithms with their high-throughput VLSI architectures for a 4×4, 64-QAM complex MIMO detector are proposed in this thesis. The proposed architectures can easily be extended to high-order constellation schemes. For the first algorithm Complexity analysis and the synthesis results in a 0.13μm CMOS technology show that compared to the reported VLSI implementations in the complex domain, the proposed architecture has the lowest silicon area and highest throughput. The proposed architecture is fully parallel and it has a fixed critical path independent of the constellation order, which can achieve to a high throughput up to 1Gbps. In the second scheme a novel hard-output detection algorithm for the complex MIMO detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, an SNR-independent fixed-throughput, and the lowest normalized energy reported to-date. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 13Gbps in a 0.13 μm CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 20Gbps. Moreover, the FPGA implementation of the proposed algorithm on Virtex-4 XC4VFX140 proves the sustained throughput of 2.2Gbps at 90.5MHz clock frequency. The proposed architecture can be tailored for low-power/lower-area applications at the expense of a lower detection throughput.

  9. Keywords:
  10. Multiple Input Multiple Output (MIMO)System ; Very Large Scale Integration (VLSI)Circuits ; Throughput ; Complex-Domain Detection

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