Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since...
Reliable communication has become very crucial in the transmission applications. Hence, to design hardware to handle reliability is the most important part of communication. In this work, we propose a new secured ALU (Arithmetic and Logic Unit) against fault attacks that is used in ARM processor which can correct any 5-bit error in any position of 32-bit input registers of ALU. We also designed a BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) using the prototyping FPGA. Further, in this thesis we designed (63, 36) the BCH encoding and decoding system to tolerate the 5-bit faults. The codec system and ALU system are based on using Verilog description language. Since...