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Analytical Approaches for Soft Error Rate Estimation of Digital Circuits and Circuit Level

Ahmadyan, Nematollah | 2011

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 41981 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. The aggressive device scaling and exponential increase in transistor counts on a chip have increasingly made the modern integrated circuits more susceptible to soft errors. Soft errors are caused by strikes from energetic particles such as neutrons and alpha particles. These errors are making a significant impact in the microelectronics industry. An essential step to design a highly reliable digital system with minimal performance and power penalty is Soft Error Rate (SER) estimation of system components.We propose a very fast and accurate analytical approach to estimate the overall SER and to identify the most vulnerable gates, flip-flops, and paths of a circuit. Our proposed approach fully supports Single and Multiple Event Transients fault models for single and multi cycles of circuit operation; Also the proposed approach accurately computes all four masking factors, namely, logical, electrical, and timing and application masking. Unlike previous approaches, the proposed approach firstly does not rely on fault injection or fault simulation; SERs estimated by the proposed approach for some ISCAS89 circuit benchmarks are compared with that estimated by the Monte Carlo (MC) simulation based fault injection approach. The results show that the proposed approach is about four orders of magnitude faster than the MC fault injection approach while having an accuracy of about 96%. This level of fastness and accuracy makes the proposed approach a viable solution to measure the SER of very large size circuits used in industry
  9. Keywords:
  10. Dependability Evaluation ; Soft Error Rate (SER) ; Soft Error Rate Estimation

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