Hierarchical Fat-tree Topology for an Optical Network-on-Chip, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
With increasing number of processors on a chip, the role of interconnections becomes more important in both power consumption and bandwidth. As a result, in MultiProcessor System-on-Chip architectures, the design constraints will shift from "Computational Constraints" to "Communicational Constraints". Nowadays, optical information transfer is introduced as a suitable substitution for electrical interconnections in chips, which can eliminate their problems. Many different optical networks have been presented so far. These networks can be divided into two subcategories. Networks of the first category use an electrical infrastructure as well as optical one. Hence, the scalability of scheme is...
Cataloging briefHierarchical Fat-tree Topology for an Optical Network-on-Chip, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shahin (Supervisor)
Abstract
With increasing number of processors on a chip, the role of interconnections becomes more important in both power consumption and bandwidth. As a result, in MultiProcessor System-on-Chip architectures, the design constraints will shift from "Computational Constraints" to "Communicational Constraints". Nowadays, optical information transfer is introduced as a suitable substitution for electrical interconnections in chips, which can eliminate their problems. Many different optical networks have been presented so far. These networks can be divided into two subcategories. Networks of the first category use an electrical infrastructure as well as optical one. Hence, the scalability of scheme is...
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