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VLSI Architecture Implementation for a 4×4 MIMO Detector Applied to the LTE

Neshatpour, Katayoun | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 43138 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Shabany, Mahdi
  7. Abstract:
  8. Long Term Evolution (LTE), is a standard for wireless communication of high-speed data for mobile phones and data terminals. Increasing the capacity, improved support for mobility and simplified architecture are a number of its goals. As many other standardas LTE uses Multiple Input-Multiple Output (MIMO), which is a system that uses multple antennas in the transmitter and the reciver. LTE has adopted single carrieer-frequency division multiple access (SC-FDMA) for the uplink multiple access scheme in order to decrease peak to average power ratio (PAPR). In SC-FDMA a discrete Fourier transform (DFT) is performed on the signlas before going through the OFDMA modulation.
    A novel low-complexity detection scheme is proposed for the multiple-input multiple-output MIMO SC-FDMA systems, which is suitable for ASIC implementations. The proposed detection scheme makes an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) frequency domain equalizer (FDE) detector and finds symbols with higher error probability among them and browse more candidates for them in the constellation to improve their initial estimate. Based on this approach, an architecture is introduced that achieves superior bit error rate (BER) performance compared to the conventional MMSE FDE. The performance of the proposed design is close to the existing maximum likelihood-post detection processing (ML-PDP) scheme, while achieving a significantly lower complexity , i.e., 450× less Euclidean distance (ED) calculations in 16-QAM. The ASIC implementation of the proposed architecture, the first ASIC for SC-FDMA detectors to-date, achieves a 3× higher throughput than the best design reported to-date [32]. The ASIC implementation and the FPGA testing of the algorithm is done for both 16-QAM and 64-QAM modulation scheme. Moreover an iterative detection scheme is proposed that upgrades the performance of the detector without affecting the throughput. The ASIC implementation of the proposed algorithm is done for the 16-QAM modulation scheme
  9. Keywords:
  10. Multiple Input Multiple Output (MIMO)System ; Long Time Evolution (LTE)Standard ; Single Carriere-Frequancy Division Multiple Access (SCFDMA)

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