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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 43161 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Hajsadeghi, Khosrow
- Abstract:
- Analog to digital converters are one of the most important component of Bluetooth and GSM receivers. The pipeline and Successive Approximation Register (SAR) ADCs are mainly used in these receivers. However, the pipeline ADCs consume lots of power and SAR ADCs suffer the resolution in advanced technologies. On the other hand, the Delta-Sigma ADCs are capable of achieving high resolution with a low power. So in this thesis, the various kinds and different implementations of Delta-Sigma Modulators are introduced. The system level design and the conversion between Discrete-Time Modulators and Continuous-Time Modulators are explained. The non-ideality effects such as limited gain and bandwidth of op-amp, clock jitter, excess loop delay, and DAC errors are discussed. The 12 bit Continuous-Time with 500 KHz signal bandwidth for the GSM and Bluetooth applications is designed in 01.8 um CMOS technology. Thea power consumption is optimized by using a new architecture of 2bit per step SAR ADC instead of conventional flash ADC as a quantizer. The simulations show the modulator consumes 1.42mw power with 64.8 dB SNDR at 500 KHz signal bandwidth
- Keywords:
- Delta-Sigma Modulator ; Successive Approximation Register (SAR) ; Low Power Modulator ; Continuous-Time Sigma-Delta Modulator ; Excess Loop Delay ; Discrete Time Modulator
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