Low power Clock and Data Recovery Circuits in 20Gb/s Range in CMOS Technology

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Parkalian, Nina | 2012

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 43341 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Hajsadeghi, Khosrow
Abstract:
Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been proposed which reduces the problem of jitter enhancement in this structures. Circuit design has been done in 0.18µm CMOS technology for 20Gb/s input data. Post layout simulations show the power consumption of the circuit is 67mW and the jitter of the recovered clock is 5.9ps
Keywords:
Clock and Data Recovery Circuit ; Phase Locked Loop (PLL) ; Phase Detector ; Timing Jitter ; Voltage Controlled Oscillator

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