Speed Optimization In Hardware Implementation Of JPEG2000

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Bayat, Mina | 2013

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 44241 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Vosughi Vahdat, Bijan
Abstract:
According to needs for high quality pictures with high compression, in variety of applications such as Satellite communications, in this thesis some parts of JPEG2000 standard with computation and time complexity, have been implemented on FPGA. This parts are:
1- Two dimensional Discrete wavelet transform (2D-DWT)
2- Bit Plan Coding
3- Context-based Adaptive Binary Arithmetic Coding (MQ-Coder)
Each of these parts is implemented on basis of the best architectures in papers with some improvement on its hardware; and the results are compared with other similar works. Other parts, such as “Packet Creation” that are intrinsically software-based, are not implemented and it is better to be implemented by a processor. In this thesis, simulations have been done in Modelsim and our synthesis tool is Xilinx ISE
Keywords:
Compression ; Joint Photo Graphic Expert (JPEG)Processor ; Bit-Plane Coding ; MQ Encoder ; Two Dimentional Discrete Wavelet Transform (2D-OWT)

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