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Design and Implementation of a Spectrum Sensor for Cognitive Radio

Safavi, Mahya | 2012

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44305 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Shabani, Mahdi
  7. Abstract:
  8. Frequency scarcity has emerged the necessity of opportunistic utilization of frequency bands, which can be realized through a cognitive radio system. During an agile communication between unlicensed users, a cognitive radio system must avoid collision with licensed users. Hence it should continuously observe the band of interest and report the presence of licensed user signals. This task is fulfilled by a vital part of a cognitive radio system, called the spectrum sensing core. Recently several techniques have been proposed for the spectrum sensing in literature. Some of them like matched filtering, cyclostationarity based detection are based on primary user signal features. However energy detection (ED)and eigenvalue based detection (EBD) are among blind sensing methods. The focus of this thesis is on proposing an efficient VLSI implementation of a sensitive blind sensing technique to be used in negative SNR regimes. Simulation results show that eigenvalue based sensing has a significantly better performance compared to energy detection with respect to the probability of detection in noise uncertainty condition at SNRs below zero. However since using filters to channelize the input signal has an adverse effect on eigenvalue based sensing, it has not been used in high-resolution sensing regimes. In this thesis, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. Moreover, using an EBD approach overcomes the SNR wall problem and enables detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time VLSI architecture is developed for the algorithm, which is implemented in a 0.18 um CMOS technology. The implemented design occupies a total area of 3.4mm2 and dissipates 142mW for a 40 MHz sensing bandwidth consisting of 32 sub-channels. To verify the functionality of the designs, all of them were tested on ML605 as evaluation board of virtex 6 FPGA
  9. Keywords:
  10. Cognitive Radio ; Spectrum Sensing ; Very Large Scale Integration (VLSI)Circuits

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