RT-Level Test Pattern Generation with Horner Expansion Model, Ph.D. Dissertation Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Navabi, Zainalabedin (Co-Advisor)
Abstract
Increasing in size and complexity of digital designs has made manufacturing process more complex and enforces more complexity in verification of designs. This makes it essential to address critical verification issues at the early stages of design cycle. Such a complicated designs needs to be tested for fabrication faults as well as functional faults. Several attempts have been made to raise the quality of testing methods with automatic test pattern generation (ATPG) and design for testability (DFT) methods in logic and lower levels. Although these techniques try to increase the testability of a circuit considerably, but there are always some overheads in area, power and performance....
Cataloging briefRT-Level Test Pattern Generation with Horner Expansion Model, Ph.D. Dissertation Sharif University of Technology ; Tabandeh, Mahmoud (Supervisor) ; Navabi, Zainalabedin (Co-Advisor)
Abstract
Increasing in size and complexity of digital designs has made manufacturing process more complex and enforces more complexity in verification of designs. This makes it essential to address critical verification issues at the early stages of design cycle. Such a complicated designs needs to be tested for fabrication faults as well as functional faults. Several attempts have been made to raise the quality of testing methods with automatic test pattern generation (ATPG) and design for testability (DFT) methods in logic and lower levels. Although these techniques try to increase the testability of a circuit considerably, but there are always some overheads in area, power and performance....
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