Deign of 10 Bit 200 MS/s Pipeline Analog to Digital Converter in 0.18 um, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosro (Supervisor)
Abstract
High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... Cataloging briefDeign of 10 Bit 200 MS/s Pipeline Analog to Digital Converter in 0.18 um, M.Sc. Thesis Sharif University of Technology ; Haj Sadeghi, Khosro (Supervisor)
Abstract
High speed data converter are very often used in telecommunication systems. Since these systems are increasingly used in mobile foem reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate 200MS/s with a power consumption of 35 mW for the input level of 1Vp-p and a 1.8V power supply in 0.18um CMOS technology.
To reach these goals, a number of low power techniqes are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors is optimized analytically which leads to simple back-envelope formulas to calculate the optimum values. In circuit level, a... Find in contentBookmark |
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