Low-power Design of Decimal Multipliers

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Malekpour, Amin | 2013

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 44644 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Ejlali, Ali Reza
Abstract:
Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require their data to be precise while binary number system cannot ensure precision. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today’s digital systems. Hence, in this thesis we present a comparative study of parallel decimal multipliers, considering energy/power consumption (leakage and dynamic power consumption), latency and area. Furthermore, we present two novel techniques to reduce energy/power consumption of parallel decimal multipliers. One leads to 9.1% power consumption reduction and 6.1% energy consumption reduction for parallel decimal multipliers and the other, in the best case, leads to 8.8% power consumption reduction and 11.1% energy consumption reduction for full adder cells
Keywords:
Energy Consumption ; Power Consumption ; Decimal Multiplication ; Parallel Multiplier ; Full Adder

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