Low-power Design of Decimal Multipliers, M.Sc. Thesis Sharif University of Technology ; Ejlali, Ali Reza (Supervisor)
Abstract
Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require their data to be precise while binary number system cannot ensure precision. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today’s digital systems. Hence, in this thesis we present a comparative study of parallel decimal multipliers, considering energy/power consumption (leakage and dynamic power consumption), latency and area. Furthermore, we present two novel techniques to reduce energy/power consumption of...
Cataloging briefLow-power Design of Decimal Multipliers, M.Sc. Thesis Sharif University of Technology ; Ejlali, Ali Reza (Supervisor)
Abstract
Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require their data to be precise while binary number system cannot ensure precision. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today’s digital systems. Hence, in this thesis we present a comparative study of parallel decimal multipliers, considering energy/power consumption (leakage and dynamic power consumption), latency and area. Furthermore, we present two novel techniques to reduce energy/power consumption of...
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