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Design of Clock and Data Recovery Circuits Inmulti Gb/s Range in CMOS Technology

Jafarbeiki, Sara | 2013

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 44767 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): HajSadeghi, Khosrow
  7. Abstract:
  8. Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
    In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider (ILFD) is used as an ILO (injection-locked oscillator), so that the output frequency of the oscillator is half of the bit rate. The input data rate is 20 Gb/s and the output clock frequency is set at 10 GHz which is half of the bit rate. Complementary clocks are used to drive two flip flops in the decision circuit to retime the data. A new approach is also used to accommodate temperature and process variations. By using this approach lock range increased to a value of 1.5GHz. The circuit is designed in 0.18 um CMOS. The circuit simulation shows that the power consumption is 55.3 mW at 20Gb/s which shows a significant power reduction
  9. Keywords:
  10. Injection Locking ; Phase Detector ; Clock and Data Recovery Circuit ; Voltage Controlled Oscillator ; Timing Jitter ; Complementary Metal Oxide Semiconductor Technology (CMOS)

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