A Communication Model between SIMT Cores for Improving GPU Performance, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
In recent years, GPUs are becoming an ideal candidate for processing a variety of high performance applications. By relying on thousands concurrent threads in applications and the computational power of large numbers of computing units; GPGPUs have provided high performance and throughput. To achieve the potential computational power of GPGPUs in broader kinds of applications, we need to apply some modifications in their architecture. In the baseline architecture, the maximum part of chip area is devoted to SIMT cores which their communication is handled through an interconnection network and a slow off-chip memory. Recent research shows that out of many types of miss events the last level...
Cataloging briefA Communication Model between SIMT Cores for Improving GPU Performance, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shahin (Supervisor)
Abstract
In recent years, GPUs are becoming an ideal candidate for processing a variety of high performance applications. By relying on thousands concurrent threads in applications and the computational power of large numbers of computing units; GPGPUs have provided high performance and throughput. To achieve the potential computational power of GPGPUs in broader kinds of applications, we need to apply some modifications in their architecture. In the baseline architecture, the maximum part of chip area is devoted to SIMT cores which their communication is handled through an interconnection network and a slow off-chip memory. Recent research shows that out of many types of miss events the last level...
Find in contentBookmark |
|