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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 45051 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Shabany, Mahdi
- Abstract:
- Long Term Evolution (LTE) aims the peak data rates in excess of 300 Mb/s, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. One efficient approach to achieve this throughput is by parallelizing the Log Maximum a Posteriori (MAP) algorithm in the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this thesis, first, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design requires no memory or QPP inverse to perform deinterleaving and has been fully implemented and tested both on a Virtex-6 FPGA as well as in a 0.18 um CMOS process. Second, a new property of the QPP interleaver, called the correlated shifting property, is theoretically proved, leading to a fully scalable interleaver and a low-complexity memoryless address generator for an arbitrary order of parallelism. The proposed interleaver reduces the required addresses in half, making the realized address generator in a 0.13 um CMOS technology to achieve at most 19.6% less area compared to the best reported work to-date. Furthermore, as opposed to other designs, it works for all possible block sizes. Third, the two main challenging computational units in MAP core are both alpha and beta recursion units. Although many works have been proposed to shorten the critical path of the recursion units, an efficient architecture which can perform computation with minimum silicon area is still missing. In this thesis, the relation between both the alpha and beta metrics are presented, leading to a novel add-compare-select (ACS) unit. The proposed ACS implementation results on the LTE turbo codes achieve 18% less area compared to the conventional implementation in 0.13 um CMOS technology. Finally, the novel technique, referred to as data interleaving, is used to highly pipeline the forward and backward recursion units without any performance lost. The proposed methods lead to an efficient high-throughput log-MAP decoder to meet the LTE requirements
- Keywords:
- Turbo Decoder ; Interleaver ; Very Large Scale Integration (VLSI)Circuits ; Soft-Input Decoding ; Hard-Input Decoding ; Long Time Evolution (LTE)Standard
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