VLSI Architecture of Turbo Decoder for LTE, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor)
Abstract
Long Term Evolution (LTE) aims the peak data rates in excess of 300 Mb/s, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. One efficient approach to achieve this throughput is by parallelizing the Log Maximum a Posteriori (MAP) algorithm in the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this thesis, first, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS)...
Cataloging briefVLSI Architecture of Turbo Decoder for LTE, M.Sc. Thesis Sharif University of Technology ; Shabany, Mahdi (Supervisor)
Abstract
Long Term Evolution (LTE) aims the peak data rates in excess of 300 Mb/s, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. One efficient approach to achieve this throughput is by parallelizing the Log Maximum a Posteriori (MAP) algorithm in the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this thesis, first, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS)...
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