Design of Power Distribution Network in 3D ICs Thesis Submitted, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we...
Cataloging briefDesign of Power Distribution Network in 3D ICs Thesis Submitted, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we...
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